Flip-flop arrangement for a divide-by-2 frequency divider comprising master-slave type memory elements

Flip-flop arrangement for halving a frequency of a signal received on an input terminal, comprising:

• a RS-flip-flop with a first and a second logic gate that have their first gate inputs mutually intercoupled to their gate outputs;
• a third logic gate and a fourth logic gate having respective gate outputs coupled to a second gate input of the first and the second logic gate, respectively, and having first gate inputs coupled to a gate output of the second and first logic gate, respectively, via a conduction path of a first and a second switch, respectively the second gate inputs of the third and fourth logic gates and control inputs of switches being coupled to said input terminal.