Reset signal generating circuit

A reset signal generating circuit comprising:

• voltage dividing means for dividing a power source voltage into a divided voltage;
• first switching means coupled to said voltage dividing means, said first switching means being turned ON when the power source voltage rises to a value in a vicinity of a predetermined value with an arbitrary rising speed;
• second switching means coupled to an output of said first switching means, said second switching means being turned ON during a time in which said first switching means is ON;
• and
• charging and discharging means including a capacitor which is supplied with an output signal of said second switching means for starting a charging operation from a first time when said second switching means turns ON, said charging and discharging means outputting a reset signal for a constant time from said first time to a second time and stopping to output the reset signal after said second time,
• said second switching means including a metal oxide semiconductor (MOS) transistor having a source supplied with the output signal of said first switching means, a first inverter supplied with the output signal of said first switching means, a first capacitor having one terminal supplied with the power source voltage and another terminal coupled to an output terminal of said first inverter, a second inverter supplied with an output signal of said first inverter, and a second capacitor having one terminal coupled to an output terminal of said second inverter and another terminal coupled to a ground, said output terminal of said second inverter being coupled to a gate of said MOS transistor, said output signal of said second switching means being obtained from a drain of said MOS transistor.