Self-correcting semiconductor memory device and microcomputer incorporating the same
AssigneeOki Electric Industry Co., Ltd.
InventorsKikuzo Sawada, Kouzi Tanagawa, Nobuhiro Tomari, Tomoaki Yoshida
Life of this patent
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Abstract
In a nonvolatile memory device or a microcomputer with a nonvolatile memory, data errors arising from loss of charge in the floating gates of memory cells are detected and corrected by applying two different sense voltages to the memory cells and comparing the outputs. Instead of using a cumbersome error-correcting code, this error-correcting scheme requires only one parity bit per word, yet it can detect and correct errors in any odd number of bits. Benefits include reduced chip size and longer life for electrically erasable and programmable memories.
Claims23
A self-correcting semiconductor memory device comprising:
- a memory cell array having sets of cells, each set comprising data cells for storing data bits and a parity cell for storing a parity bit for detecting bit errors generated by said data cells;
- selection means for selecting an arbitrary set of cells;
- read-out means for applying a first sense voltage to the selected set of cells to produce first read data comprising data bits and a parity bit;
- parity checking means for checking the parity of the first read data and producing an output indicating whether a parity error is present;
- said read-out means capable of applying a second sense voltage of a level different from the level of said first sense voltage to said selected set of cells to produce second read data comprising data bits and a parity bit;
- and
- correction means for receiving the read data and producing correct read data, said correction means correcting any error in the data bits of the read data responsive to the read data and the output of the parity checking means.
A microcomputer comprising:
- a memory cell array having sets of cells, each set comprising data cells for storing data bits and a parity cell for storing a parity bit for detecting bit errors generated by said data cells;
- selection means for selecting an arbitrary set of cells;
- read-out means for applying a first sense voltage to the selected set the data cells and the parity cell to produce first read data comprising data bits and a parity bit;
- parity checking means for checking the parity of the first read data and producing an output indicating whether a parity error is present;
- said read-out means capable of applying a second sense voltage of a level different from the level of said first sense voltage to said selected set of cells to produce second read data comprising data bits and a parity bit;
- and
- correction means for receiving the read data and producing correct read data, said correction means correcting any error in the data bits of the read data responsive to the read data and the output of the parity checking means.
Dependencies are inferred from the claim text.