Integrated data and timing circuitry for automatic circuit tester

An apparatus, including apparatus terminals adapted for connection of an electronic circuit thereto, for applying signals to and/or sensing signals at the apparatus terminals, the apparatus comprising:

• A. a clock for generating a master clock signal comprising periodically occurring pulses;
• and
• B. a data/timing channel associated with each terminal, each channel comprising:
• i. a leading-edge memory and a trailing-edge memory, each given memory including an ordered plurality of memory locations, operable by application of respective individual clock signals thereto to produce, in response to the occurrence of each pulse in the respective individual clock signal, an output signal determined by the contents of the next location in the given memory and occurring at a time determined by the time of occurrence of the respective individual-clock-signal pulse;
• and
• ii. individual-clock-signal means responsive to the master clock signal for applying to the leading-edge memory and the trailing-edge memory a respective individual clock signal containing a pulse in response to each pulse in the master clock signal;
• and
• iii. a formatter connected to receive the outputs of the leading-edge and trailing edge memories for performing one of (a) applying to its respective terminal signal pulses whose leading edges are determined by the times of occurrence of transitions in the output of the leading-edge memory and whose trailing edges are determined by the times of occurrence of transitions in the output of the trailing-edge memory and (b) testing for the presence at the associated terminal, at points in a time determined by the times of occurrence of transitions in the leading-edge-memory and the trailing-edge-memory outputs, of signals having values determined by the leading-edge-memory and the trailing-edge-memory outputs.