Digital FIFO memory
AssigneeDeutsche ITT Industries GmbH
InventorUlrich Theus
Life of this patent
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Abstract
A digital FIFO memory is disclosed which is formed by a memory cell array (zf) comprising of n signal channels (b1 . . . bn) each containing m memory cells (c..1, c..2, c..m-1, c..m) are first, second, and mth clock drivers (tt1, tt2, ttm-1, ttm), respectively, which are controlled by a basic clock signal (g1) and further signals. Thus FIFO memory makes it possible to pass an input data stream arriving at an input data rate (g2) through the FIFO memory in such a way that the output data stream appears at the output (da) at an output data rate (g3) momentarily different from the input data rate (g2). On a time average, however, the two data rates are equal, so that data can be written into and read from the FIFO memory simultaneously at different rates.
Claims18
A digital FIFO memory comprising:
- insulated-gate field-effect transistors and a memory cell array (zf) of n parallel signal channels (b1 . . . bn) having their inputs connected to the data input (de) of the memory and having their outputs coupled to the data output (da) of the memory;
- each signal channel containing m series-connected, identical memory cells (c . . . ) each having an enable input;
- and
- clock signals being applied to the memory cells in so that memory cells which are adjacent in the direction of signal flow are rendered conductive one after the other;
- wherein the input of the respective signal channel is connected directly to the data input (de), and the output to the data output (da);
- wherein a first clock driver (tt1), a second clock driver (tt2), and an mth clock driver (ttm-1, ttm) are associated with the n first memory cells (c . . . 1), the n second memory cells (c . . . 2), and the n mth memory cells (c . . . m-1, c . . . m), respectively;
- wherein the m clock drivers (tt . . . ), which are identical in construction, are fed a reset signal (rs) and a basic clock signal (g1) whose frequency is greater than twice the maximum input data rate (g2);
- wherein each clock driver (tt . . . ) has a reset input (rs), and data availability input line (ve) and a data availability output line (va), with the data availability input line (ve) of a clock driver (tt2) connected to the data availability output line (va) of the directly preceding clock driver (tt1), as well as a data request input line (re) and a data request output line (ra), with the data request input line (re) of a clock driver (tt1) connected to the data request output line (ra) of the following clock driver (tt2);
- wherein the data availability input line (ve) of the first clock driver (tt1) has a signal applied thereto which indicates the presence of valid input data;
- and
- wherein the data request input line of the last clock driver (ttm) has a signal applied thereto which indicates that a next data word has to be transferred to the output.
Dependencies are inferred from the claim text.