Dynamic random-access memory system with power-up and power-down refresh circuits
AssigneeInternational Computers Limited
InventorsJonathan M. Hanbury, Keith Burton
Life of this patent
Estimating the term…
Abstract
A dynamic random-access memory (DRAM) has a first refresh circuit for producing memory refreshes during power-up, and a second refresh circuit for producing memory refreshes during power-down. The power-down refresh circuit is powered by a battery, and has a lower power consumption than the power-up circuit. During transition from power-down to power-up, the frequency of refreshing is doubled for a short period, so as to build up a surplus of refreshes. This allows refreshing to stop while the first or power-up refresh circuit is brought back into operation.
Claims5
A dynamic random-access memory system comprising:
- (a) a dynamic random-access memory,
- (b) means for generating control signals defining a power-down condition, a transition condition, and a power-up condition,
- (c) a power-down refresh circuit, responsive to said control signals, for producing a series of refresh signals at a first predetermined frequency in the power-down condition and at a second predetermined frequency in the transition condition, the second predetermined frequency being higher that the first predetermined frequency,
- (d) a power-up refresh circuit for producing a series of refresh signals in the power-up condition, the power-up refresh circuit having a higher power requirement than the power-down refresh circuit, and
- (e) selection means, responsive to said control signals, for selecting refresh signals from the power-down refresh circuit to determine refresh cycles for the memory during the power-down condition and the transition condition, and for selecting refresh signals from the power-up refresh circuit to determine refresh cycles for the memory during the power-up condition.
A method of operating a dynamic random-access memory system comprising a dynamic random-access memory, a main power supply, a back-up power supply, a power-up refresh circuit, and a power-down refresh circuit having a lower power requirement than the power-up refresh circuit, the method comprising:
- (a) operating the system in a power-down condition in which the main power supply is inactive and the power-down refresh circuit receives power from the back-up power supply,
- (b) in the power-down condition, operating the power-down refresh circuit to supply refresh signals to the memory at a first predetermined frequency, to determine refresh cycles for the memory,
- (c) activating the main power supply,
- (d) during a first transitional period following activation of the main power supply, operating the power-down refresh circuit to supply refresh signals to the memory at a second predetermined frequency, higher than the first predetermined frequency,
- (e) during a second transitional period following said first period, initializing said power-up refresh circuit, without supplying any refresh signals to the memory,
- (f) during a third transitional period, following the second period, operating the power-up refresh circuit to supply refresh signals to the memory at said second predetermined frequency, and
- (g) following said third period, operating the system in a power-up condition, in which the power-up refresh circuit supplies refresh signals to the memory at said first predetermined frequency.
Dependencies are inferred from the claim text.