Semiconductor memory device having two column transfer gate transistor groups independently provided for a sense amplifier and a programmed circuit

A semiconductor memory device into which an externally generated datum is programmed by an externally generated programming address signal when said memory device is in a programming mode, and from which a datum, stored in said memory device, is read out by an externally generated reading address signal when said memory device is in a reading mode, said memory device comprising:

• a plurality of word-lines;
• a plurality of bit-lines extending across said word-lines to form a plurality of intersection points;
• a plurality of memory cells formed at said intersection points;
• a column decoder means for providing a first column selecting signal in response to said programming address signal when said memory device is in said programming mode, and for providing a second column selecting signal in response to said reading address signal when said memory device is in said reading mode;
• a programming circuit for providing a selected memory cell with a data signal corresponding to said externally generated datum when said memory device is in said programming mode;
• a sense amplifier for amplifying a data signal obtained from said datum read out from a selected memory cell when said memory device is in said reading mode;
• a plurality of metal-oxide semiconductor (MOS) first column transfer gate transistors connected between said programming circuit and said plurality of bit lines, respectively, for selectively connecting a selected bit-line to said programming circuit in response to said first column selecting signal during said programming mode, said first column transfer gate transistors being made non-conductive during said reading mode;
• and
• a plurality of metal-oxide semiconductor (MOS) second column transfer gate transistors connected between said sense amplifier and said plurality of bit lines, respectively, for selectively connecting a selected bit-line to said sense amplifier in response to said second column selecting signal during said reading mode, wherein the current carrying capacity of each of said first column transfer gate transistors is greater than that of each corresponding second column transfer gate transistor.