Bloch-line memory element and ram memory

A random access bi-stable Bloch-line memory system having a standard deviation of the switching field below 5 percent comprising:

• XY discrete memory elements arranged electrically in an X row, Y column matrix array, each memory element formed a magnetizable material having a bi-stable Bloch-line formed therein ;
• a plurality of discrete low resistance coupling elements serially electrically coupling Y discrete memory elements for forming Y discrete memory elements per memory column;
• column/row read means for coupling a column read current to a selected one of said Y memory columns, said column read current signal serially flowing through said discrete low resistance electrically intercoupling elements and said electrically intercoupled X discrete memory elements therebetween as determined by selection means;
• and
• readout means coupled to the one selected memory element at the intersection of the one selected row line and the one selected memory column for determining by circuit electrical resistance and the presence or absence of a Bloch-line disposed within the sensing area on the discrete memory element.

A Bloch-line random access memory system having a standard deviation of the switching field below 5 percent with the capability of writing data in and non-destructively reading data out, comprising:

• a memory including a plurality of juxtaposed columns of memory cells arranged in an array having a plurality of juxtaposed rows of conductors operatively connected to a plurality of juxtaposed columns of conductors for writing into the memory cells and reading out of the memory cells logic "ones" and logic "zeros" wherein the presence of a bi-stable Bloch-line in a predetermined sensing area of the memory element corresponds to one of the logic states and the absence of the Bloch-line within the predetermined sensing area corresponds to the other of the logic states;
• row means operatively connected to the plurality of juxtaposed rows of conductors for selecting and driving a particular one thereof during a write or read operation based on a predetermined address;
• column means operatively connected to the plurality of juxtaposed columns of conductors and the plurality of juxtaposed columns of memory cells for selecting and driving a particular one of the juxtaposed meandering columns of conductors during a write operation or a read operation based on a predetermined address;
• said row means and said column means cooperating during the write operation to generate coincident drive currents the polarities and amplitudes of the drive currents depending on whether a logic "zero" or a logic "one" is to be written, and said column means cooperating during the read operation to enable a current flow through the particular selected one of the memory elements;
• and
• data readout means the input of which is operatively connected to the plurality of juxtaposed columns of memory cells of said memory element such that when the particular one of the plurality of juxtaposed columns of memory cells is selected and the particular one of the plurality of juxtaposed rows of conductors is selected, the logical contents of memory cell at that location is read by determination of the electrical resistance of the cell depending on the presence or absence of a Bloch-line within the sensing area of the memory element.