Multiple-stage carry-select adder having unique construction for initial adder cells

An adder for processing n-bit-wide operands (a,b) with the assistance of n/m adder stages, each having a processing width of m-bits for m-bit-wide sub-operands, each adder stage comprising in combination:

• (a) an initial adder coil (AZA) for the least significant bit of a sub-operand and m-1 normal adder cells (AZN), constructed alike, one each for the remaining bits of the sub-operand;
• (b) each adder cell (AZA, AZN) being connected to receive a first carry-in signal and a second carry-in signal from a next-lower adder cell, to generate a sum signal (S) from the operand bits supplied to it and from one of said carry-in signals, and to generate a first carry-out signal and a second carry-out signal, said carry-out signals are supplied to a next adder cell of this stage or the initial adder cell of the next higher adder stage as said carry-in signals;
• (c) said initial adder cell having means for generating said sum signal by selecting one of said carry-in signals supplied to it in response to a first selection signal, said carry-in signals are permanently set to logic 0 at the least significant adder stage, otherwise the carry signals are supplied from the next-lower stage, for generating a second selection signal for the next higher adder stage by transferring from said initial adder cell to the next higher adder stage, the carry-in signal which is used to generate the sum signal, for generating a first carry-out signal by an AND operation from the operand bits supplied to it and a second carry-out signal by an OR-operation of said operand bits;
• (d) each normal adder cell (AZN) having means for generating said sum signal by selecting one of said carry-in signals supplied to it in response to said second selection signal, for generating carry-out signals which are identical to said received carry-in signals when the supplied operand bits have different logic values, which are logic 0 when both operand bits are logic 0 and which are logic 1 when both operand bits are logic 1, for transferring the second selection signal to the next adder cell of said stage or to the initial adder cell of the next higher adder stage as said first selection signal.