Multiple function data processor

A reconfigurable processor, comprising:

• a first ALU including first, second and output N-bit ports and a carry input terminal;
• a second ALU including first, second and output N/2-ports, carry input and output terminals;
• a third ALU including first, second and output N/2-bit ports, and a carry output terminal;
• controllable coupling means coupled to said carry input terminals of said first and second ALUs and to said carry output terminals of said second and third ALUs for selectively coupling said carry output terminal of said third ALU to said carry input terminal of said second AL and said carry output terminal of said second ALU to said carry input of said first ALU;
• means for applying (a), in a first mode of operation, the N-bit MSB of a first 2N-bit word to said first input port of said first ALU and the N-bit MSB of a second 2N-bit word to said second input port of said first ALU, and the N/2-bit LSB of said first 2N-bit word to said first input port of said third ALU and the N/2-bit LSB of said second 2N-bit word to said second input port of said third ALU, and the remaining N/2 bits of said first 2N-bit word to said first input port of said second ALU and the remaining N/2 bits of said second 2N-bit word to said second input port of said second ALU, (b) in a second mode of operation, a first N-bit word to said first input port of said first ALU and a second N-bit word to said second input port of said first ALU, and the N/2 most significant bits of a third N-bit word to said first input port of said second ALU and the N/2 most significant bits of a fourth N-bit word to said second input port of said second ALU, and the N/2 least significant bits of said third N-bit word to said first input port of said third ALU and the N/2 least significant bits of said fourth N-bit word to the second input port of said third ALU, (c) in a third mode of operation, the N most significant bits of 3N/2-bit mantissa of a first floating-point word to said first input port of said first ALU and the N most significant bits of the 3N/2-bit mantissa of a second floating-point word to said second port of said first ALU, and the N/2-bit least significant bits of said 3N/2-bit mantissa of said first floating-point word to said first input port of said second ALU, and the N/2 least significant bits of said second floating-point word to said second input port of said second ALU, and the N/2-bit exponent of said first floating-point word to said first input port of said third ALU, and the N/2-bit exponent of said second floating-point word to said second input port of said third ALU;
• and
• means for controlling said controllable coupling means for, (a) in said first mode of operation, coupling said carry output terminal of said third ALU to said carry input terminal of said second ALU and said carry output terminal of said second ALU to said carry input terminal of said first ALU, (b) in said second mode of operation, decoupling said carry output terminal of said second ALU from said carry input terminal of said first ALU and coupling said carry output terminal of said third ALU to said carry input terminal of said second ALU, and (c) in said third mode of operations coupling said carry output terminal of said second ALU to said carry input terminal of said first ALU and decoupling said carry output terminal of said third ALU from said carry input terminal of said second ALU.

An arrangement for processing data having a number of bits equal to N1+N2+N3, which data is produced at an N1-bit first source port and an (N2+N3)-bit second source ports, and which data is configurable in the form of an N1+N2+N3 - bit word, or two N1 - bit words, or a word including an (N1+N2) bit mantissa with N3 - bit exponent, comprising:

• an N1 - bit register file including a first N1-bit input port and a second (N2+N3)-bit input port and first, second, third, fourth, fifth and sixth output ports, said first and second output ports each having N1 bits, said third and fourth output ports having N2 and N3 bits, respectively, which together constitute one output port, with said third output port representing the most significant of said N2+N3 bits, and said fourth output port representing the remaining bits of lesser significance, said fifth and sixth output ports having N2 and N3 bits, respectively, which together constitute one output port, with said fifth output port representing the most significant bits, and said sixth output port representing the remaining bits of lesser significance;
• a dynamically reconfigurable arithmetic logic unit including first and second input ports coupled to a first portion of said arithmetic logic unit, said first and second input ports of said first portion of said arithmetic logic unit each having N1 bits and being coupled to said first and second output ports of said register file, respectively, said first portion of said arithmetic logic unit further including a carry input terminal and an N1-bit output port, said reconfigurable arithmetic logic unit further including third and fourth input ports coupled to a second portion of said arithmetic logic unit, said second portion of said arithmetic logic unit further including a carry input terminal, a carry output terminal, and an N2 -bit output port, said third input port of said arithmetic logic unit having N2 bits and being coupled to said third output port of said register file, said fourth input port of said arithmetic logic unit having N2 bits and being coupled to said fifth output port of said register file, said reconfigurable arithmetic logic unit further including fifth and sixth input ports coupled to a third portion of said arithmetic logic unit, said third portion of said arithmetic logic unit further including a carry output terminal and an N3 - bit output port, said fifth input port of said arithmetic logic unit having N3 bits and being coupled to said fourth output port of said register file, and said sixth input port of said arithmetic logic unit having N3 bits and being coupled to said sixth output port of said register file, said reconfigurable arithmetic logic unit further including first and second controllable switch means, said first switch means including a controllable path coupled to said carry output terminal of said second portion of said arithmetic logic unit and to said carry input terminal of said first portion of said arithmetic logic unit, said second switch means including a controllable path coupled to said carry output terminal of said third portion of said arithmetic logic unit and to said carry input terminal of said second portion of said arithmetic logic unit, said first and second switch means each further including control input terminals;
• coupling means coupled to said first and second input ports of said register file and adapted to be coupled to said first and second source ports for coupling data from said first and second source ports to said first and second input ports of said register file, respectively;
• switch control means coupled to said first and second switch means for controlling said switch means in at least first, second and third operating modes, said first operating mode having said first and second switch means closed for thereby operating said first, second and third portions of said arithmetic logic unit together as an (N1+N2+N3) - bit arithmetic logic unit, said second operating mode having said first switch means open and said second switch means closed for thereby operating said first portion of said arithmetic logic unit independently and for operating said second and third portions of said arithmetic logic unit together as an (N2+N3) - bit portion, said third operating mode having said first switch means closed and said second switch means open for thereby forming an (N1+N2) - bit portion of said arithmetic logic unit including said first and second portions of said arithmetic logic unit together with a separate N3 - bit portion including said third portion of said arithmetic logic unit.