Floating point circuit with configurable number of multiplier cycles and variable divide cycle ratio

In a circuit having a multiplier unit and a divide and square root unit, both said units being coupled to receive operands from a multiplier circuit for selecting operands, said multiplier receiving a system clock signal from a clock circuit, the improvement comprising:

• means, coupled to said clock circuit, for providing a divide clock signal to said divide and square root unit, said divide clock signal having a frequency which is an integral multiple, other than one, of a frequency of said system clock signal;
• means, coupled to an input of said divide and square root unit, for synchronizing a data input of said divide and square root unit to said system clock signal and said divide clock signal;
• and
• means, coupled to an output of said divide and square root unit, for synchronizing a data output of said divide and square root unit to said system clock signal and said divide clock signal.

In a circuit having a multiplier, an arithmetic logic unit, a divide and square root unit and means for providing a primary cycle clock, said multiplier having a first stage including an input register, a second stage including a multiplexer coupled to said input register and a multiplexer array coupled to said multiplexer, and a third stage including man output register or latch coupled to said multiplier array, the improvement comprising:

• a latch having an input coupled to an output of said multiplier array;
• a first data bus coupling an output of said latch to an input of said multiplexer;
• a second data bus coupling said multiplier array directly to said output register;
• means, coupled to said means for providing a primary cycle clock, for selectively providing said primary cycle clock or a fraction of said primary cycle clock to a clock input of said latch;
• means for providing a divide clock to said divide and square root unit, said divide clock having a frequency which is an integral multiple of a frequency of said primary cycle clock;
• means for synchronizing a data input of said divide and square root unit to said primary cycle clock and said divide clock;
• and
• means for synchronizing a data output of said divide and square root unit to said primary cycle clock and said divide clock.

A method for adjusting the latency mode of a multiplier circuit having a first stage including an input register, a second stage including a multiplexer coupled to said input register and a multiplier array coupled to said multiplexer, and a third stage including an output register or latch coupled to said multiplier array, comprising the steps of:

• providing a latch having an input coupled to an output of said multiplier array;
• providing a first data bus coupling an output of said latch to an input of said multiplexer;
• providing a second data bus coupling said multiplier array directly to said output register;
• and
• providing one of a primary clock signal or a fraction of said primary clock signal to a clock input of said latch.

A method for providing a selectable frequency divide clock in a circuit having a multiplier unit and a divide and square root unit, both said units being coupled to a multiplexer circuit for selecting operands, said multiplier receiving a system clock from a clock circuit, comprising the steps of:

• providing a divide clock to said divide and square root unit, said divide clock having a frequency which is an integral multiple, other than one, of a frequency of said system clock;
• synchronizing a data input of said divide and square root unit to said system clock and said divide clock;
• and
• synchronizing a data output of said divide and square root unit to said system clock and said divide clock.