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US 4,901,264 AGranted
Pseudo random pattern generating device
AssigneeAdvantest Corporation
InventorMishio Hayashi
Life of this patent
Estimating the term…
Abstract
A pseudo random pattern generating device generates a pseudo random pattern, which recurs on a cycle of (2.sup.n -1) bits. The device sequentially converts from parallel to serial form 2.sup.m -bit patterns read out of a pattern memory having stored at each address a subpattern composed of one of 2.sup.n-m split patterns. A basic pseudo random pattern is split at intervals of 2.sup.m bits and a continuation pattern of a predetermined number of bits subsequent to each split pattern in the recurring random pattern. A pattern of 2.sup.m bits to be taken out of each subpattern which is read out of the pattern memory is shifted one bit position upon each readout of 2.sup.n-m subpatterns.
Claims10
A pseudo random pattern generating device comprising:
- pattern memory means wherein there are stored at 2.sup.n-m addresses for 2.sup.n-m subpatterns of at least (2.sup.m+1 -1) bits in length, where n is an integer equal to or greater than 3 and m is a positive integer smaller than n, each of the subpatterns being composed of one of 2.sup.n-m split patterns into which a pseudo random pattern, which recurs on a cycle of (2.sup.2 -1 ) bits, is split at intervals of 2.sup.m bits, starting at the beginning of the pseudo random pattern, and a continuation pattern of a predetermined number of bits subsequent to said each split pattern in the recurring pseudo random pattern;
- a 2.sup.n-m counter which counts a clock and sequentially outputs the count values as address signals;
- readout means which is supplied with the address signals one after another, for reading out the subpatterns stored in said pattern memory means at addresses corresponding to the address signals, in synchronism with the clock;
- shift means for outputting a pattern composed of a contiguous 2.sup.2 bits in each of the subpatterns read out by said readout means from the addresses, while circularly shifting in a rightward direction the 2.sup.m -bit pattern to be output by one bit position in the subpatterns upon each readout of the 2.sup.n-m subpatterns;
- latch means for latching the 2.sup.m -bit pattern output from said shift means;
- and
- parallel-serial converting means which is supplied with the 2.sup.2 -bit pattern in parallel form from said latch means, for outputting the 2.sup.m -bit pattern as a serial pattern.
4 more elements
A pseudo random pattern generating device comprising:
- a memory for storing, as one word, 2.sup.n-m subpatterns of 2.sup.m+1 bits in length, where n is an integer equal to or greater than 3 and m is a positive integer smaller than n, each of the subpatterns being composed of one of a plurality of split patterns into which a pseudo random pattern, which recurs on a cycle of (2.sup.n -1) bits, is split at intervals of 2.sup.m bits and a continuation pattern of 2.sup.m bits subsequent to said each split pattern;
- an address counter, coupled to said memory, for counting clocks up to 2.sup.n-m, respectively and providing the count value as an address signal to said memory;
- a shift register, coupled to said memory, for inputting thereinto in parallel a pattern read out of said memory for each clock;
- means for circularly shifting the pattern input into said shift register by one bit position in a leftward direction to produce a shifted pattern;
- means for writing the shifted pattern into said memory;
- a latch, coupled to said shift register, for latching a pattern composed of 2.sup.m bits at the leftmost 2.sup.m bit positions of the pattern in said shift register by the clock after the shifted pattern has been written into said memory;
- a parallel-serial converter, coupled to said latch, for converting the latched pattern into a serial pattern;
- a 2.sup.n counter for counting clocks up to 2.sup.n ;
- means for switching over the leftmost 2.sup.m bits and the rightmost 2.sup.m bits of each output pattern from said memory in response to an overflow of said 2.sup.n counter;
- and
- means responsive to the output of said 2.sup.n counter for additionally incrementing said address counter by one, for additionally inputting in parallel an additionally read-out pattern from said memory into said shift register, for additionally shifting said parallel-input pattern one bit position, and for additionally causing said write means to write said shifted pattern.
8 more elements
A pseudo random pattern generating device comprising:
- a memory which stores therein 2.sup.n-m subpatterns each of (2.sup.m+1 -1) bits in length, where n is an integer equal to or greater than 3 and m is a positive integer smaller than n, each of the subpatterns being composed of one of a plurality of split patterns into which a pseudo random pattern, which recurs on a cycle of (2.sup.n-1) bits, is split at intervals of 2.sup.m bits and a continuation pattern of (2.sup.m -1) bits subsequent to said each split pattern;
- a 2.sup.n-m counter, coupled to said memory, for counting a clock and providing the count value as an address signal to said memory;
- a 2.sup.m counter, coupled to said 2.sup.n-m counter, for counting a carry of said 2.sup.n-m counter;
- a multiplexer having inputs connected to parallel (2.sup.m+1 -1)-bit outputs of said memory, and having control terminals coupled to said 2.sup.m counter for receiving therefrom the count value as a control input, and which produces as an output, in accordance with the control input, one of 2.sup.m combinations of patterns of sequentially contiguous 2.sup.m bits in a (2.sup.m+1 -1)-bit pattern read out of said memory using the address signal supplied from said 2.sup.n-m counter;
- a latch, coupled to said multiplexer, into which the output of said multiplexer is input upon each generation of said clock;
- a parallel-serial converter, coupled to said latch, for converting the output of said latch into a serial pattern;
- and
- means for incrementing said 2.sup.n-m counter by one upon each generation of an output of said 2.sup.m counter.
5 more elements
Dependencies are inferred from the claim text.