US 4,901,230 A · Computer vector multiprocessing control with multiple access memory and priority conflict resolution method

Abstract

A multiprocessing system and method for multiprocessing is disclosed. A pair of processors are provided, and each are connected to a central memory through a plurality of memory reference ports. The processors are further each connected to a plurality of shared registers which may be directly addressed by either processor at rates commensurate with intra-processor operation. The shared registers include registers for holding scalar and address information and registers for holding information to be used in coordinating the transfer of information through the shared registers. A multiport memory is provided and includes a conflict resolution circuit which senses and prioritizes conflicting references to the central memory. Each CPU is interfaced with the central memory through three ports, with each of the ports handling different ones of several different types of memory references which may be made. At least one I/O port is provided to be shared by the processors in transferring information between the central memory and peripheral storage devices. A vector register design is also disclosed for use in vector processing computers, and provides that each register consist of at least two independently addressable memories, to deliver data to or accept data from a functional unit. The method of multiprocessing permits multitasking in the multiprocessor, in which the shared registers allow independent tasks of different jobs or related tasks of a single job to be run concurrently, and facilitate multithreading of the operating system by permitting multiple critical code regions to be independently synchronized.

Claims12

Dependent claims

A multiprocessor memory system comprising:

a central memory comprised of a plurality of independently addressable memory banks organized into a plurality of sections each accessible through a plurality of access paths;
a plurality of processing machines;
each of said processing machine including a plurality of ports for generating memory references to any one of said central memory sections;
and
conflict resolution means interfacing each of said ports to each of said central memory sections through said central memory access paths, said resolution means for receiving references from said ports and coordinating and controlling the procession of said references along to said access paths, said conflict resolution means comprising a plurality of conflict resolution circuits corresponding in number to said memory sections, each of said circuits receiving said references to its corresponding section from any one of said ports and selectively conveying said references to said access paths for said corresponding section, said circuits each including;
means for checking the readiness of said memory banks to be referenced and holding a reference to a busy one of said banks until said bank is ready to be referenced;
means for detecting when more than one of said references is pending to the same bank simultaneously and holding all but one of said simultaneously pending references;
and
means communicating with said ports and the other of said conflict resolution circuits to cause one of said ports referencing said memory to suspend generation of further references when a reference from said referencing port is being held and to cause the other of said conflict resolution circuits which have received a subsequent reference from said referencing port issued subsequent to a held reference generated by said referencing port to hold said subsequent reference until all priorly generated references from said referencing port have proceeded so that references to the memory are kept in the order generated.

6 more elements

A multiprocessor memory system comprising:

a central memory comprised of a plurality of independently addressable memory banks organized into a plurality of sections each accessible through a plurality of access paths;
a plurality of procesing machines equal in number to said plurality of access paths;
each of said processing machines including a plurality of ports for generating memory references to any one of said central memory sections, each of said ports responsive to a port conflict signal to hold further generation of references until the port conflict signal is removed;
and
conflict resolution means interfacing each of said ports to each of said central memory sections through said central memory access paths, said resolution means for receiving references from said ports and coordinating and controlling the procession of those references along to the access paths, said conflict resolution means comprising a plurality of conflict resolution circuits corresponding in number to said memory sections, each of said circuits connected to each of said ports for said processing machines so that any port in any one of said processing machines may access any section and bank in said central memory, said circuit organized so that all references from ports in a given processing machine are directed through a single one of said access paths so that each processing machine has a corresponding access path, each of said circuits including:
(a) bank busy signal means for determining and signalling which banks in its corresponding section of memory are busy;
(b) bank busy conflict detection means connected to said bank busy signal means for detecting when a port is attempting to reference a busy bank and generating a corresponding bank busy conflict signal;
(c) inter-processing machine simultaneous reference conflict checking means for determining simultaneous attempts by ports of different processing machines to reference the same bank and generating a corresponding simultaneous reference conflict signal;
(d) a conflict resolution sub-circuit for each port connected to said circuit, said sub-circuit connected to receive said bank busy conflict signals and said simultaneous reference conflict signal, said sub-circuit including:
(i) means responsive to said bank busy conflict signal for holding a reference attempting to proceed to a busy bank;
(ii) means for generating a port conflict signal whenever a reference is held from proceeding to the memory;
(iii) means responsive to port conflict signals generated by other corresponding subcircuits in other conflict resolution circuits for holding further references from the port if a port conflict signal is received so that references from the same port of the same processing machine are prevented from proceeding out of the order generated by the port;
(e) each of said circuits further including means for determining if more than one port from a processing machine is attempting a reference to an available bank in the section and choosing the highest priority port to proceed on the corresponding access path and holding the other reference or references, a port without a simultaneous reference conflict and having an odd address increment having priority over a port with an even address increment and if both ports have the same address increment the port which was earliest activated having priority, said chosen reference proceeding only if a port conflict signal from another resolution circuit is not present.

10 more elements

A method of conveying memory references from the processing machines to the central memory and resolving memory reference conflicts in a multiprocessor memory system, said system including:

a central memory having a plurality of independently addressable memory banks organized into a plurality of sections each accessible through a plurality of access paths;
a plurality of processing machines;
each of said processing machines including a plurality of ports for generating memory references to any of said central memory sections and banks;
a conflict resolution circuit for each section of memory for interfacing each of said ports from said processing machines to the corresponding section of memory, said resolution circuit providing one access path to the memory section for each processing machine in the system so that all ports of a given processing machine reference a given section of memory through the same access path;
within a conflict resolution circuit, said method comprising the steps of:
(a) receiving memory reference requests from said ports;
(b) determining for each reference request which of said memory banks within the memory section associated with said conflict resolution circuit has been requested;
(c) checking the status of said requested memory bank to determine whether said bank is ready to be referenced or whether said bank is busy;
(d) determining whether there are simultaneous reference requests to the memory section associated with said conflict resolution circuit from multiple ports of the same processing machine;
(e) determining whether there are simultaneous reference requests to any one bank within the memory section associated with said conflict resolution circuit from ports of different processing machines;
(f) resolving bank busy conflicts, conflicts between simultaneous references from ports of the same processing machine and conflicts between simultaneous references from ports of different processing machines so that only one memory reference to any one memory bank is allowed at one time, only one memory reference to the memory section associated with said conflict resolution circuit from any one processing machine is allowed at one time, and all memory references from any one port proceed in the order in which the references were generated.

8 more elements

A method of conveying memory references from the processing machines to the central memory and resolving memory reference conflicts in a multiprocessor memory system, said system including:

a central memory having a plurality of independently addressable memory banks organized into a plurality of sections each accessible through a plurality of access paths;
a plurality of processing machines;
each of said processing machines including a plurality of ports for generating memory references to any of said central memory sections and banks;
a conflict resolution circuit for each section of memory for interfacing each of said ports from said processing machines to the corresponding section of memory, said resolution circuit providing one access path to the memory section for each processing machine in the system so that all ports of a given processing machine reference a given section of memory through the same access path;
within a conflict resolution circuit, said method comprising the steps of:
(a) receiving memory reference requests from said ports;
(b) determining for each reference request which of said memory banks within the memory section associated with said conflict resolution circuit has been requested;
(c) checking the status of said requested memory bank to determine whether said bank is ready to be referenced or whether said bank is busy;
(d) comparing the requested memory banks of memory reference requests received simultaneously from different processing machines to determine whether a memory bank conflict exists as between simultaneously pending references from different processing machines;
(e) determining whether more than one port of the same processing machine has simultaneously referenced the memory section associated with said conflict resolution circuit;
(f) assigning priority between the ports of the same processing machine, a port with an odd address increment having priority over a port with an even address increment and where both ports have the same increment the earliest activated port reference having priority;
(g) assigning priority between the processing machines on an alternating basis;
(h) handling memory references from ports so that a port with no bank busy conflict, no simultaneous reference from a different processing machine conflict and no conflict with another port of the same processing machine is allowed to proceed;
(i) handling conflicts between ports of the same processing machine so that the highest priority port with no bank busy conflict and no simultaneous reference from a different processing machine conflict is allowed to proceed;
(j) handling simultaneous references from different processing machines conflicts so that the port of the highest priority processing machine with no bank busy conflict and no conflict with another port of the same processing machine is allowed to proceed;
(k) holding references which have a bank busy conflict or have a conflict with a higher priority port or have a conflict with a port of a higher priority processing machine;
and between different conflict resolution circuits, said method comprising the step of:
(l) preventing references generated by the same port of a processing machine from proceeding out of order.

15 more elements

A multiprocessor memory system comprising:

a central memory comprised of a plurality of independently addressable memory banks organized into a plurality of sections each accessible through a plurality of access paths;
a plurality of processing machines equal in number to said plurality of access paths;
each of said processing machines including a plurality of ports for generating memory references to any one of said central memory sections;
and
conflict resolution means interfacing each of said ports to each of said central memory sections through said central memory access paths, said resolution means for receiving references from said ports and coordinating and controlling the procession of those references along to the access paths, said conflict resolution means comprising a plurality of conflict resolution circuits corresponding in number to said memory sections, each of said circuits connected to each of said ports for said processing machines so that any port in any one of said processing machines may access any section and bank in said central memory, said circuit organized so that all references from ports in a given processing machine are directed through a single one of said access paths so that each processing machine has a corresponding access path, each of said circuits including:
(a) bank detection means for determining which of said memory banks within the memory section associated with said circuit has been requested;
(b) bank busy conflict means for determining whether the requested memory bank is ready to be referenced or is busy;
(c) means for determining whether said circuit has received simultaneous reference requests to the memory section associated with said circuit from multiple ports of the same processing machine;
(d) means for determining whether said circuit has received simultaneous reference requests to any one bank within the memory section associated with said circuit from ports of different processing machines;
(e) resolution means for resolving bank busy conflicts, conflicts between simultaneous references from ports of the same processing machine, and conflicts between simultaneous references from ports of different processing machines so that only one memory reference to any one memory bank is allowed at one time, only one memory reference to the memory section associated with said circuit from any one processing machine is allowed at one time, and all memory references from any one port proceed in the order in which the references were generated.

7 more elements

Dependencies are inferred from the claim text.

Computer vector multiprocessing control with multiple access memory and priority conflict resolution method

Life of this patent

Computer vector multiprocessing control with multiple access memory and priority conflict resolution method

Life of this patent

Abstract

Claims12