Pipelined cache system using back up address registers for providing error recovery while continuing pipeline processing
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorTakashi Kodama
Life of this patent
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Abstract
A cache memory includes an address back-up register for storing the physical address of the data where errors are generated for backing up the address register, a data array address back-up register for storing data address of the data where errors are generated for backing up the data array address register, and a request code back-up register for storing a preceding request code at the time of the error generation. When an error is detected by the system controller, data is read from the main memory according to the back-up registers and the control register, EYCY register and PSEDO ACK register, of the system controller.
Claims7
A non-interruptive, pipelined cache memory for use in a data processing system including a central processing unit and a main memory connected to said central processing unit via a system bus, which comprises:
- an address converter connected to said address bus for converting a logical address into a physical address;
- at least one address array for storing a physical address from said main memory;
- at least one data array for storing data from said main memory corresponding to said physical address stored in said address array;
- an address register for storing a physical address from said address converter;
- a data array address register for storing a data address of data stored in said data array;
- at least one comparator for comparing a physical address from said address converter with a physical address from said address array to produce either a cache hit signal which causes said data in said data array to be read out on said system bus or a cache miss signal which causes a block of data to be loaded in said data array from said main memory;
- an error detector for detecting generation of an error in data from said data array and generating an error signal at detection;
- address back-up register means connected to said address register for storing a physical address of said data from said data array in response to said error signal;
- data array address back-up register means connected to said data array address register for storing a data address of said data from said data array in response to said error signal;
- and
- a system control unit which comprises means for enabling the transfer of said physical address from said address register to said address back-up register means and said data address from said data array register to said data array address back-up register means and means for enabling a physical address of a next request to be stored in said address register now empty and a data address of said next request to be stored in said data array address register so that data is read out of said main memory without interrupting a pipeline operation of said cache memory.
A non-interruptive, pipelined cache memory for use in a data processing system which includes a central processing unit and a main memory connected to said central processing unit via a system bus, which comprises:
- an address converter connected to said address bus for converting a logical address into a physical address;
- at least one address array for storing a physical address from said main memory;
- at least one data array for storing data from said main memory corresponding to said physical address stored in said address array;
- an address register for storing a physical address from said address converter;
- a data array address register for storing a data address of data stored in said data array;
- at least one comparator for comparing a physical address from said address converter with a physical address from said address array to produce either a cache hit signal which causes said data in said data array to be read out on said system bus or a cache miss signal which causes a block of data to be loaded in said data array from said main memory;
- an error detector for detecting generation of an error in data from said data array and generating an error signal at detection;
- address back-up register means connected to said address register for storing a physical address of said data from said data array in response to said error signal;
- data array address back-up register means connected to said data array address register for storing a data address of said data from said data array in response to said error signal;
- request code back-up register means connected to said system bus for storing REQ and CODE signals in response to said error signal;
- and
- a system control unit which comprises means for enabling the transfer of said physical address from said address register to said address back-up register means and said data address from said data array register to said data array address back-up register means and means for enabling a physical address of a next request to be stored in said address register now empty and a data address of said next request to be stored in said data array address register so that data is read out of said main memory without interrupting a pipeline operation of said cache memory.
Dependencies are inferred from the claim text.