Method and apparatus for backing out of a software instruction after execution has begun

In a data processing system for performing operations on operands as specified by instructions, apparatus for initializing execution of instructions whose operation is aborted, said apparatus comprising:

• control store means for storing sequences of control signals for controlling operation of said system as specified by said instructions, said control store means having address inputs connected to receive said instructions as address inputs and outputs for providing said sequences of control signals and being addressed by said instructions to provide from said outputs a first sequence of said control signals for controlling said execution of said instructions;
• register file means having address inputs coupled from said control signal outputs of said control store means and data inputs and data outputs for storing and receiving memory addresses of operands and being addressed by said control signal outputs of said first sequence of said control signals for storing and providing a first memory address for a first operand, said first memory address having a first low order portion and a first high order portion;
• stack means having data inputs coupled to said register file means data outputs and having address inputs connected from said control signal outputs and being addressed by said control signals of said first sequence for storing said first low order portion of said first memory address;
• memory means having address inputs coupled to said register file means data outputs for receiving said memory address and generating an interrupt signal if said first operand is not stored in said memory means, said interrupt signal indication that said operation of said instruction is aborted,
• arithmetic means having data inputs connected from said data outputs of said register file means and data outputs connected to said data inputs of said register file means and control input connected from said control signal outputs,
• said arithmetic means being controlled by said control signals of said first sequence to receive said memory address and increment or decrement said first memory address as controlled by said control signals to generate a a second memory address of a second operand stored in said memory means, said second memory address having a second low order portion and a second high order portion;
• said register file means being addressed by said control signal outputs of said first sequence of said control signals for storing said second memory address in place of said first memory address;
• said control store means having an address input connected from said memory means for receiving said interrupt signal and being addressed by interrupt signal for providing a second sequence of control signals;
• said data inputs of said arithmetic means being further coupled to data outputs of said stack means, said register file means and said stack means being addressed by said control signals of said second sequence to respectively provide said first low order portion and a second order portion from said second memory address to said data inputs of said arithmetic means, and said arithmetic means being controlled by said control signals of said second sequence of control signals to receive said first low order portion and a second low order portion and generate a carry signal if said second low order portion was smaller than said first low order portion;
• said control store means having an address input connected to receive said carry signal and being addressed by said carry signal to provide a third sequence of control signals, and
• said register file means being addressed by said third sequence of control signals for replacing said second memory address in said register file means by said first memory address.