Signal processing system for large screen display apparatus

A display apparatus having a plurality of picture elements (2) each capable of having any one of plural display gradations, said apparatus comprising:

• a display means (4) in which picture elements (2) are arranged in a matrix form of 2.sup.a .times.2.sup.b picture elements, where a and b are integers;
• a frame memory (15) for storing c-bit data representing one of 2.sup.c different gradations for each said picture element where c is an integer, said frame memory responding to an address input of (a+b) bits to provide a c-bit data output corresponding to a picture element identified by said (a+b)-bit address input;
• and
• a clock signal source for providing a clock signal;
• an address control section (18) for frequency-dividing said clock signal successively by factors ranging from 1/2 to (1/2).sup.a+b+c to obtain an output of (a+b+c) bits, wherein (a+b) of said output bits from said address control section correspond to one of said (2.sup.a +2.sup.b) picture elements in said display means and determine said (a+b)-bit address input to said frame memory, and wherein c of said output bits from said address control section identify a reference signal level corresponding to one of said 2.sup.c display gradations available for each picture element;
• an on-off decision section (16) for performing a comparison of the c-bit data output from said frame memory with said reference level and for producing 1-bit data output representing "on" and "off" states of said picture elements in accordance with results of said comparison;
• and
• timing control means (FIG. 15) for applying said 1-bit data to said picture elements and holding said 1-bit data for a predetermined period of time to drive said display means;