Multi-chip interconnection package

A semiconductor interconnection package comprising:

• a chip-holding frame having opposed, planar major surfaces, a plurality of holes extending through said frame between said major surfaces, said holes housing a power conducting feedthrough and a ground conducting feedthrough, each of said feedthroughs having opposed ends situated substantially flush with said major surfaces;
• a plurality of integrated circuit chips carried in openings within said frame, said chips having planar opposed major faces, one of said faces including terminal pads including ground and power pads;
• and
• a multilayer substrate supporting said chips, said substrate having an exterior flat surface to which said frame is attached and comprising an insulating wafer having a ground conductor layer, a power conductor layer, and an insulator layer deposited thereover and interposed between said frame and said wafer, said power and ground conductor layers separated from each other by said insulator layer, a first set of conductive vias for electrically coupling said ground conductor layer to said ground pads through said ground conducting feedthroughs, and a second set of conductor layer to said power pads through said power feedthroughs.