Semiconductor memory

A semiconductor memory which includes a plurality of word lines, a plurality of bit lines, and a plurality of memory cells, each memory cell including an insulated-gate field-effect transistor and a capacitor, wherein said insulated-gate field-effect transistor comprises:

• a gate electrode electrically connected to one of the plurality of word lines, wherein the gate electrode comprises at least one material selected from polycrystalline silicon, molybdenum silicide, molybdenum, and tungsten,
• a source and drain provided in a semiconductor surface region having first conductivity type, one of the plurality of bit lines being connected to the drain or source of the insulated-gate field-effect transistor, wherein the drain or source of the insulated-gate field-effect transistor is commonly formed between predetermined pairs of adjacent ones of said plurality of memory cells, and
• a gate insulation film provided between the semiconductor surface region and the gate electrode, the gate insulation film being formed less than 50 nm;
• and
• wherein said capacitor comprises:
• a groove formed into the semiconductor surface region, wherein a depth of the groove is more than 1 .mu.m, wherein the depth of the groove is greater than a distance between inner walls of the groove, and wherein the semiconductor surface region surrounding the groove acts as a first electrode,
• a capacitor insulation film formed on a surface of the groove, wherein the capacitor insulation film comprises a composite film of SiO.sub.2 and Si.sub.3 N.sub.4, and
• a second electrode formed in the groove over the capacitor insulation film, the second electrode being connected to the source or drain of the insulated-gate field-effect transistor, wherein the second electrode comprises a polycrystalline silicon, and wherein the groove is filled with the second electrode,
• wherein an individual groove is provided for forming the capacitor for each memory cell.

A semiconductor memory which includes a plurality of word lines, a plurality of bit lines, and a plurality of memory cells, each memory cell including an insulated-gate field-effect transistor and a capacitor, wherein said insulated-gate field-effect transistor comprises:

• a gate electrode electrically connected to one of the plurality of word lines, wherein the gate electrode comprises at least one material selected from polycrystalline silicon, molybdenum silicide, molybdenum, and tungsten,
• a source and drain provided in a semiconductor surface region having a first conductivity type, one of the plurality of bit lines being connected to the drain or source of the insulated-gate field-effect transistor, wherein the drain or source of the insulated-gate and field-effect transistor is commonly formed between predetermined pairs of adjacent ones of said plurality of memory cells, and
• a gate insulation film provided between the semiconductor surface region and the gate electrode;
• and
• wherein said capacitor comprises:
• a groove formed into the semiconductor surface region, wherein a depth of the groove is more than 2 .mu.m, the depth of the groove is greater than a distance between inner walls of the groove, and the semiconductor surface region surrounding the groove acts as a first electrode, wherein the first electrode comprises an impurity region formed into the semiconductor surface region, wherein the region is commonly formed between predetermined pairs of adjacent ones of said plurality of memory cells,
• a capacitor insulation film formed on a surface of the groove, wherein the capacitor insulation film comprises a three-layer composite film of SiO.sub.2, Si.sub.3 N.sub.4, SiO.sub.2, and
• a second electrode formed in the groove over the capacitor inulation film, the second electrode being connected to the source or drain of the insulated-gate field-effect transistor,
• wherein an individual groove is provided for forming the capacitor for each memory cell.