US 4,901,076 AGranted

Circuit for converting between serial and parallel data streams by high speed addressing

AssigneeInternational Business Machines Corporation

InventorsHaluk O. Askin, Frank D. Ferraiolo

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Abstract

A circuit for converting a multi-bit data signal from a first format to a second format. The circuit includes an input for receiving the multi-bit data signal in a first format, an output for providing the multi-bit data signal in a second format, and a ring counter having a number of stages for providing, in sequential order, stage output signals. A format conversion device connected between the input and the output has a number of latches with each latch being connected to the input for simultaneously receiving data bits of the multi-bit data signal in the first format. A control circuit is provided for controlling the latching of selected data bits in each of the latches, and a transmission circuit is provided between the latches and the output for transmitting the bits latched in the latches to the output responsive to the stage output signals of the ring counter, thereby placing the multi-bit data signal in the second format.

Claims26

Dependent claims

A circuit for converting a multi-bit data signal from a first format to a second format, said circuit comprising:

input means for receiving said multi-bit data signal in said first format;
output means for providing said multi-bit data signal in said second format;
ring counter means having a plurality of stages, each stage having an output, the outputs of said plurality of stages for providing, in sequential order stage output signals;
format conversion means connected between said input means and said output means, said format conversion means having a plurality of latches, each latch being connected to said input means for simultaneously receiving data bits of the multi-bit data signal in said first format, control means for controlling the latching of selected data bits from said input means into each of said latches, and transmission means between said latches and said output means for sequentially transmitting the bits latched in said latches to said output means responsive to being addressed by the sequential stage output signals of said ring counter means, thereby placing the multi-bit data signal in said second format;
clock means having an input terminal for receiving a timing signal, said timing signal timing the bit times of said multi-bit signal either received by said input means or output by said output means in a serial format, said clock means further having an output terminal for producing a clock signal having one clock transition for each bit time of said timing signal;
each of said plurality of stages comprising a latch having a D input, a Q input, and a C input, said C input connected to the output terminal of said clock means, the Q output of each of said latches being connected to the D input of the latch of the succeeding stage for shifting a counter signal from stage to stage;
and
initial signal means connected to the D input of the latch of the first stage of said ring counter for starting said counter signal being shifted from stage to stage, wherein a shift of said counter signal occurs from one stage to the succeeding stage for each clock transition of said clock signal.

5 more elements

A circuit for converting a multi-bit data signal from a first format to a second format, said circuit comprising:

input means for receiving said multi-bit data signal in said first format;
output means for providing said multi-bit data signal in said second format;
ring counter means having a plurality of stages each stage having an output, the outputs of said plurality of stages for providing, in sequential order stage output signals;
and
format conversion means connected between said input means and said output means, said format conversion means having a plurality of latches, each latch being connected to said input means for simultaneously receiving data bits of the multi-bit data signal in said first format, control means for controlling the latching of selected data bits from said input means into each of said latches, and transmission means between said latches and said output means for sequentially transmitting the bits latched in said latches to said output means as said latches are addressed by the sequential stage output signals of said ring counter means, thereby placing the multi-bit data signal in said second format;
said output means includes driver means having a plurality of input terminals for together receiving said multi-bit data signal in a parallel format from said format conversion means, and a plurality of output terminals for together providing said multi-bit data signal in the parallel format received on its input terminals;
each of said latches in said format conversion means comprises a C input for receiving its respective stage output signal from said ring counter means, a D input connected to said input means for receiving said multi-bit data signal in a serial format, and a Q output, each of said latches reading the bit value of said multi-bit data signal on its D input when the respective output signal on its clock input has a first value, and for latching therein the bit value of said multi-bit data signal on its D input when the respective stage output signal on its C input is in a transition from said first value to a second value;
and
said transmission means comprises a conductor between the Q output of each of said plurality of latches and the corresponding one of the plurality of inputs of said driver means such that the bit value latched in each of said latches is transmitted to its respective driver means input.

6 more elements

A circuit for converting a multi-bit data signal from a first format to a second format, said circuit comprising:

input means for receiving said multi-bit data signal in said first format;
output means for providing said multi-bit data signal in said second format;
ring counter means having a plurality of stages, each stage having an output, the outputs of said plurality of stages for providing, in sequential order stage output signals;
and
format conversion means connected between said input means and said output means, said format conversion means having a plurality of latches, each latch being connected to said input means for simultaneously receiving data bits of the multi-bit data signal in said first format, control means for controlling the latching of selected data bits from said input means into each of said latches, and transmission means between said latches and said output means for sequentially transmitting the bits latched in said latches to said output means responsive to being addressed by the sequential stage output signals of said ring counter means, thereby placing the multi-bit data signal in said second format;
said input means includes a plurality of input terminals for together receiving said multi-bit data signal in a parallel format, and a plurality of output terminals for together providing said multi-bit data signal in the parallel format received on its input terminals;
each of said latches in said format conversion means comprises a C input, a D input connected to a respective one of the output terminals of said input means for receiving a respective bit of said multi-bit data signal, and a Q output;
said transmission means comprises selector means having a plurality of D inputs, each D input connected to the Q output of the respective one of said latches in said format conversion means, a Q output connected to said output means, and a plurality of C inputs, each C input connected to the output of the respective one of the stages of said ring counter means such that each stage output signal from said ring counter means causes the respective bit of said multi-bit data signal received by said input means in said parallel format to be provided to said output means in a serial format;
and
said control means comprises a read signal means connected to the C inputs of said latches for latching bits on the input terminals of said input means into said latches at a time when said bits on said input terminals are valid.

7 more elements

The circuit for converting a multi-bit data signal from a first format to a second format, said circuit comprising:

a plurality of latches, each latch having a D input for receiving data bits of said multi-bit data signal in said first format, a Q output on which is placed the data bit latched in said latch, and a C input for causing the latch to latch the data bit on its D input responsive to a signal received by said C input;
ring counter means having a plurality of numbered stages, each of said stages having an output, wherein selected ones of the outputs of said stages are connected to one or more of the C inputs of said latches;
and
clock means in said ring counter means for enabling said ring counter means to place a stage output signal, one at a time and in numeric order, on the outputs of said stages for addressing said latches in sequential order such that as each addressed latch receives its respective stage output signal, it latches the data bit then on its D input and places the latched data bit on its Q output for sequentially converting said multi-bit data signal to said second format.

1 more element

Dependencies are inferred from the claim text.