US 4,901,036 A · Frequency synthesizer with an interface controller and buffer memory

Abstract

A frequency synthesizer which has at least one programmably characterized phase lock loop circuit includes a buffer memory and an interface controller responsive to operational codes received from a central controller to direct transfer of data words for characterization of the phase lock loop circuit among the at least one phase lock loop circuit, the buffer memory, and the central controller. In one embodiment, the transfer of data words between the central controller and phase lock loop circuit or buffer memory are performed serially in accordance with a prespecified protocol and governed by a clock signal generated by the central controller. Data word transfers between the buffer memory and at least one phase lock loop circuit may also be performed serially in accordance with a prespecified protocol, but may be governed autonomously by an internal clock signal generated by the frequency synthesizer.

Claims26

Dependent claims

A frequency synthesizer including at least one phase lock loop (PLL) circuit operationally characterized by a central controller to generate a synthesized channel frequency signal, said PLL circuit including at least one storage register dynamically programmable with data words which characterize the operation of said PLL circuit in generating said synthesized channel frequency signal, said frequency synthesizer comprising:

an interface controller coupled between said central controller and said at least one storage register of said PLL circuit and operative to receive operational code words and data words from said central controller;
and
a buffer memory coupled to said interface controller for storing a plurality of data words for characterizing the operation of said phase lock loop, said interface controller responsive to said operational code words received from said central controller to direct a transfer of data words between said central controller, said at least one storage register and said buffer memory.

an interface controller operative to receive operational code words, corresponding data words, and characterization data words from the central controller;
and
a buffer memory coupled to said interface controller for storing a plurality of characterization data words in a corresponding plurality of registers, each such data word corresponding to a unique characterization of operation of said PLL circuit in generating said synthesized channel frequency signal, said interface controller responsive to a first operational code word and corresponding first data word to transfer a characterization data word from said central controller to said buffer memory for storage in a register uniquely corresponding to the code of said first data word, and responsive to a second operational code word and corresponding second data word to transfer a characterization data word from a register of said buffer memory corresponding uniquely to the code of the second data word to said at least one storage register of said PLL circuit, whereby said at least one storage register of the PLL circuit is dynamically programmed with the transferred characterization data word from the buffer memory.

A frequency synthesizer including a plurality of phase lock loop (PLL) circuits, each operationally characterized by a central controller to generate a corresponding synthesized channel frequency signal, each including a storage register dynamically programmable with data words which characterize the operation of its corresponding PLL circuit in generating its synthesized channel frequency signal, said frequency synthesizer comprising:

an interface controller operative to receive operational code words, corresponding data words, and characterization data words from the central controller;
and
a buffer memory coupled to said interface controller for storing a plurality of characterization data words in a corresponding plurality of registers, each such data word corresponding to a unique characterization of operation of a PLL circuit in generating its synthesized channel frequency signal, said interface controller responsive to an operational code word and corresponding data word to direct a transfer of a characterization data word from a selected register of said buffer memory to the storage register of a selected one of said plurality of PLL circuits.

Dependencies are inferred from the claim text.

Frequency synthesizer with an interface controller and buffer memory

Life of this patent

Frequency synthesizer with an interface controller and buffer memory

Life of this patent

Abstract

Claims26