Phase-locked loop control for reading data off storage media
AssigneeAspen Peripherals Corp.
InventorBrian G. Cleveland
Life of this patent
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Abstract
An improved phase-locked loop control having a phase detector receptive of a data preamble of all "ones" from a storage sub-system for producing early and late signals to a voltage controlled oscillator in order for the frequency of the oscillator to be synchronized with the frequency of the data. A pattern detector senses the incoming preamble pulses and prevents the generation of the early and late signals when a preamble pulse is not present within a predetermined window of time.
Claims5
A phase-locked loop control having a phase detector (210) receptive of a data preamble of all "ones" from a storage sub-system (10, 30, 40, 50, 200) for producing early and late signals applied to a voltage controlled oscillator (220, 225, 230) in order for the frequency of said oscillator to be synchronized with the frequency of said data preamble, said phase detector comprising:
- means receptive of said data preamble for preventing the generation of said early and late signals when a preamble pulse (600) is not present within a predetermined window (W) of time.
A method for a phase-locked loop control having a phase detector (210) receptive of a data preamble of all "ones" from a storage sub-system (10, 30, 40, 50, 200) for producing early and late signals applied to a voltage controlled oscillator (220, 225, 230) in order for the frequency of said oscillator to be synchronized with the frequency of said data preamble, said method comprising the steps of:
- sensing the presence of said "ones" in said data preamble, and
- preventing the generation of said early and late signals when a preamble pulse (600) is not present within a predetermined window (W) of time.
A method for phase-locked loop control having a phase detector (210) receptive of a data preamble of all "ones" from a 3480 cartridge tape system (10, 30, 40, 50, 200) for producing early and late signals applied to a voltage controlled oscillator (220, 225, 230) during a high gain mode in order for the frequency of said oscillator to be synchronized with the frequency of said data preamble, said method comprising the steps of:
- sensing the presence of said "ones" in said data preamble during the high gain mode, and
- preventing the generation of said early and late signals when a preamble pulse (600) due to an error occurs before a counter reaches a first value or after the counter reaches a second value.
Dependencies are inferred from the claim text.