Frequency synthesizer with dynamically programmable frequency range of selected loop bandwith

A frequency synthesizer comprising:

• a plurality of phase lock loop (PLL) circuits, each PLL circuit governed by a respective frequency channel setting to generate a synthesized frequency signal, each PLL circuit operative in a first loop bandwidth state to maintain its synthesized frequency signal substantially at its respective frequency channel setting, each PLL circuit programmably settable randomly between old and new frequency channel settings, each PLL circuit operative in a second loop bandwidth state in response to a new frequency channel setting to converge its synthesized frequency signal to said new frequency channel setting;
• and a common bias circuit programmably operative to generate at least one bias signal which is coupled commonly to said plurality of PLL circuits for setting a common frequency range for the first and second loop bandwidth states of all of the PLL circuits.

A frequency synthesizer including:

• a phase lock loop (PLL) circuit governed by a frequency channel setting to generate a synthesized frequency signal, said PLL circuit operative in a first loop bandwidth state to maintain said synthesized frequency signal substantially at said frequency channel setting said PLL circuit programmably settable randomly between old and new frequency channel settings, said PLL circuit operative in a second loop bandwidth state in response to a new frequency channel setting to converge the synthesized frequency signal to said new frequency channel setting;
• and
• a bias circuit programmably operative to generate at least one bias signal which is coupled to said PLL circuit for setting a reference frequency range of the first and second loop bandwidth states thereof, said PLL circuit including a dynamically programmable control circuit for varying the frequency range settings of the first and second loop bandwidth states in relation to the reference frequency range set by said bias circuit.