Common-base, source-driven differential amplifier

A high speed, low noise differential amplifier comprising in combination:

• (a) a first field effect transistor having a gate coupled to a first input terminal, a source, and a drain coupled to a first supply voltage conductor, and a second field effect transistor having a gate coupled to a second input terminal, a source, and a drain coupled to the first supply voltage conductor;
• (b) a first transistor having an emitter coupled to the source of the first field effect transistor, a base, and a collector coupled to a first output terminal, and a second transistor having an emitter coupled to the source of the second field effect transistor, a base connected to the base of the first transistor, and a collector coupled to a second output terminal;
• (c) a first load device having a first terminal coupled to a second supply voltage conductor and a second terminal coupled to the collector of the first transistor, and a second load device having a first terminal coupled to the second supply voltage conductor and a second terminal coupled to the collector of the second transistor;
• (d) a bias circuit including
• i. a constant current source,
• ii. means responsive to a first input voltage applied to the first input terminal and a second input voltage applied to the second input terminal for splitting a current delivered by the constant current source into first and second currents in response to the input voltage, and
• iii. means responsive to the first and second currents for establishing a bias voltage on the bases of the first and second transistors.

A high speed, low noise differential amplifier comprising in combination:

• (a) a first field effect transistor having a gate coupled to a first input terminal, a source, and a drain coupled to a first supply voltage conductor, and a second field effect transistor having a gate coupled to a second input terminal, a source, and a drain coupled to the first supply voltage conductor;
• (b) a first transistor having an emitter coupled to the source of the first field effect transistor, a base, and a collector coupled to a first output terminal, and a second transistor having an emitter coupled to the source of the second field effect transistor, a base connected to the base of the first transistor, and a collector coupled to a second output terminal;
• (c) a first load device having a first terminal coupled to a second supply voltage conductor and a second terminal coupled to the collector of the first transistor, and a second load device having a first terminal coupled to the second supply voltage conductor and a second terminal coupled to the collector of the second transistor;
• (d) bias circuit means connected to the bases of the first and second transistors, one of the first and second supply voltage conductors, and responsive to an input signal on one of the first and second input terminals for producing a common bias voltage on the bases of the first and second transistors, thereby causing a first current to flow through the first transistor, the first load device, and the first field effect transistor, and a second current to flow through the second transistor, the second load device, and the second field effect transistor to produce a differential output signal between the collectors of the first and second transistors, the differential output signal being substantially free of any noise produced on the bases of the first and second transistors by the bias circuit means.

A high speed, low noise differential amplifier comprising in combination:

• (a) a first field effect transistor having a gate coupled to a first input terminal, a source, and a drain coupled to a first supply voltage conductor, and a second field effect transistor having a gate coupled to a second input terminal, a source, and a drain coupled to the first supply voltage conductor;
• (b) a first transistor having an emitter coupled to the source of the first field effect transistor, a base, and a collector coupled to a first output terminal, and a second transistor having an emitter coupled to the source of the second field effect transistor, a base connected to the base of the first transistor, and a collector coupled to a second output terminal;
• (c) a first load device having a first terminal coupled to a second supply voltage conductor and a second terminal coupled to the collector of the first transistor, and a second load device having a first terminal coupled to the second supply voltage conductor and a second terminal coupled to the collector of the second transistor;
• (d) bias circuit means connected to at least one of the first and second input terminals and to the bases of the first and second transistors for producing a bias voltage on the bases of the first and second transistors to cause a first current to flow through the first transistor, the first load device, and the first field effect transistor, and a second current to flow through the second transistor, the second load device, and the second field effect transistor, whereby a differential output signal produced between the collectors of the first and second transistors in response to a differential input voltage applied between the first and second input terminals is substantially free of any noise produced on the bases of the first and second transistors by the bias circuit means.