US 4,900,954 AGranted

Mixed CML/ECL macro circuitry

AssigneeSiemens Components, Inc.

InventorsMichael Franz, Tsung C. Whang

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Abstract

A circuit technique is presented for mixing current mode logic and emitter coupled logic in a manner which reduces active and passive component counts for performing recognized logic functions. The reduced counts permit greater circuit density while reducing power consumption in comparison to conventional emitter coupled logic circuitry. The mixing is also provided in a way for making all imputs and outputs compatible with conventional emitter coupled logic levels. Various logic circuits are illustrated to demonstrate the versatility of the technique. For example, a transparent high D-latch (FIG. 2), a D flip-flop with true output (FIG. 4), a two-to-one multiplex latch (FIG. 6), and other D flip-flops having set and reset inputs (FIG. 7), multiplex data inputs (FIG. 8), and Exclusive OR data inputs (FIG. 9) are circuits wherein the inventive technique is employed to advantage.

Claims20

Dependent claims

A logic network having a plurality of levels including at least one first lower current switching circuit and at least one second upper current switching circuit, each circuit comprising at least one input transistor and a reference transistor, each transistor having a base, an emitter, and a collector, the emitters of transistors in each current switching circuit connected in common together, the collector of an input transistor in each first lower current switching circuit connected to the common of a second upper current switching circuit, means for applying input signals to the bases of input transistors, means for applying first and second reference levels respectively to the base of a reference transistor in each of the at least one first lower current switching circuit and each of the at least one second upper current switching circuit, means for providing an output from at least one collector of a transistor in one second upper current switching circuit the logic network comprising:

a CML logic level including at least one CML current switch above the at least one second upper current switching circuit, each CML current switch including at least one input CML transistor and a reference CML transistor, each CML transistor having a base, an emitter, and a collector, the base of each reference CML transistor being biased at an additional reference level above the second reference level, and each CML transistor in a CML current switch having their emitters connected in common together and to a selected collector of the at least one first lower level current switching circuit, an output of each CML current switch provided at a collector of one of its CML transistors, the base of each input CML transistor in the at least one CML current switch being an input for direct connection to a selected output of the second upper level current switching circuit and the CML current switch whereby multiple CML current switches are cascaded by having inputs and outputs directly connected together.

A bipolar integrated logic circuit comprising:

a first plurality of transistors each having an input terminal, an output terminal, and a common terminal;
a first current switching logic gate including a first and second transistor of the first plurality wherein the common terminals are connected together, first means for applying a first input signal to the input terminal of the first transistor, and input terminal of the second transistor being biased by a first bias potential, one polarity of a powering potential source is applied to the output terminals;
a second current switching logic gate including a third and a fourth transistor having their common terminals connected to a current source potential coupled to receive another polarity of the powering potential source, and the third transistor having its input responsive to a second input signal and its output terminal connected to the common terminal of the first logic gate, the input terminal of the fourth transistor being biased by a second bias potential;
and
a third current switching logic gate including a fifth and a sixth transistor wherein the common terminals are connected together and to the output terminal of the fourth transistor, the input terminal of the fifth transistor is connected directly to the output terminal of the second transistor while the output of the sixth transistor provides a logic signal, the input terminal of the sixth transistor being biased by a third bias potential source above the second bias potential.

2 more elements

A logic circuit having a lower level switching gate, an intermediate level switching gate, and a first upper level switching gate, each gate comprising at least one input transistor and a reference transistor, a common terminal of each transistor in each switching gate connected together,

the lower level and intermediate level switching gates having the bases of one of its input transistors connected to receive input signals, the bases of the two reference transistors of the lower and intermediate circuits respectively being individually connected to a first bias potential and a second bias potential, the collector of the input transistor of the lower level switching gate connected to the common terminals of the transistors in the intermediate level switching gate, and
the upper current switching gate including an input transistor and a reference transistor whose base is connected to a third bias potential, their common terminals are connected together and to the collector of the reference transistor of the lower gate, the base of the input transistor is connected directly to the collector of the reference transistor of the intermediate level switching gate, and the collector of the reference transistor is coupled to the base of the input transistor and provides a logic signal whereby the logic circuit operates as a latch circuit.

Dependencies are inferred from the claim text.