Logic circuit employing field effect transistor having junction with rectifying characteristic between gate and source

A logic circuit comprising:

• a first terminal for receiving a first power source voltage;
• a second terminal for receiving a second power source voltage lower than the first power source voltage;
• a third terminal for receiving a reference voltage;
• an input terminal for receiving an input voltage;
• an output terminal for outputting an output voltage;
• a load coupled between said first terminal and said output terminal;
• and
• first and second field effect transistors coupled in series between said output terminal and said second terminal,
• said first field effect transistor being coupled to said output terminal and having a gate coupled to said third terminal,
• said second field effect transistor being coupled to said second terminal and having a gate coupled to said input terminal, said second field effect transistor having a junctin with a rectifying characteristic between the gate and source thereof,
• said output terminal outputting an output voltage having a fourth level responsive to an input voltage applied to said input terminal with a second level, outputting an output voltage having a fifth level responsive to an input voltage applied to said input terminal with a third level, and outputting an output voltage having the fourth level responsive to an input voltage applied to said input terminal with the first level, said first level being higher than said second level, said third level being an intermediate level between said first and second levels, said fourth level being higher than said fifth level.

A logic circuit comprising:

• a first terminal for receiving a first power source voltage;
• a second terminal for receiving a second power source voltage lower than the first power source voltage;
• a third terminal for receiving a reference voltage;
• an input terminal for receiving an input voltage;
• an output terminal for outputting an output voltage;
• a load coupled between said first terminal and said output terminal;
• and
• first and second field effect transistors coupled in series between said output terminal and said second terminal,
• said first field effect transistor being coupled to said output terminal and having a gate coupled to said third terminal,
• said second field effect transistor being coupled to said second terminal and having a gate coupled to said input terminal, said second field effect transistor having a junction with a rectifying characteristic between the gate and source thereof,
• said output terminal outputting an output voltage having a fourth level responsive to an input voltage applied to said input terminal with a second level, outputting an output voltage having a fifth level responsive to an input voltage applied to said input terminal with a third level, and outputting an output voltage having the fourth level responsive to an input voltage applied to said input terminal with the first level, said first level being higher than said second level, said third level being an intermediate level between said first and second levels, said fourth level being higher than said fifth level,
• said reference voltage applied to said third terminal being set to a voltage in a vicinity of a logic threshold voltage at which said input voltage changes from the second level to the third level.