US 4,900,943 AGranted

Multiplex time delay integration

AssigneeHoneywell Inc.

InventorsCharles M. Marshall, Jeffrey L. McClelland, deceased

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Abstract

A time-delay and integration arrangement for a plurality of photodetector signals which are directed alternatively along an interconnection arrangement to a corresponding set of acceptance circuit arrangements. The acceptance circuit arrangements transmit that which has been accepted through a transfer signal path to an accumulation circuit arrangement. A composite signal can then be transferred from the accumulation arrangement for further signal processing.

Claims16

Dependent claims

A method for providing time-delay integration of each of a plurality of photodetector means signals induced by electromagnetic radiation from a selected field of view impinging on an ordered array of a plurality of photodetector means, said method comprising:

directing electromagnetic radiation from a selected portion of said field of view to move across and impinge successively on each said photodetector means in said array in that order in which said photodetector means occur in said array;
providing at an output of each of said photodetector means a sequence of corresponding photodetector output indicator values with each of said photodetector output indicator values of a said photodetector means representing that amount of said electromagnetic radiation that has impinged on that photodetector means during at least part of that selected dwell duration which has elapsed since that photodetector means provided its immediately previous photodetector output indicator value;
providing during each said dwell duration conductive signal paths alternatively between each of said photodetector means outputs and inputs of a plurality of acceptance means through an input bus interconnection means electrically connected therebetween, said plurality of acceptance means each being capable of receiving over a said conductive signal path through said input bus interconnection means a representation of a said photodetector output indicator value and storing same;
providing a subsample transfer signal path through each of a plurality of subsample transfer interconnection means each electrically connected between an output of a said acceptance means in said plurality thereof and an input of a corresponding one of a plurality of accumulation means after each receipt by that said acceptance means of a said representation of a said photodetector output indicator value, said plurality of accumulation means each being capable of receiving over its subsample transfer signal path through its corresponding subsample transfer interconnection means a transfer representation of each of those said representations of said photodetector output signal indicator values received by its corresponding acceptance means, and each being further capable of combining each said subsample transfer representation received thereby in a selected accumulation number of said dwell durations, forming an accumulation period, with any said subsample transfer representations previously received in that said accumulation period to thereby provide at an output thereof a sequence of photodetector combination indicator values with each of said photodetector combination indicator values in said plurality thereof being provided in a final said dwell duration contained in each said accumulation period;
and
providing in each said final dwell duration in each said accumulation period of each accumulation means a representation of said photodetector combination indicator value at an output of a corresponding one of a plurality of sample transfer interconnection means, said sample transfer interconnection means each having its said output electrically connected to an output bus interconnection means and an input thereof electrically connected to said output of its corresponding said accumulation means.

3 more elements

A time-delay integration circuit for accumulating representations of samples of photodetector signals, said time-delay integration circuit having a signal subsample input and having an accumulated sample output, said circuit comprising:

an access switching means having an input region and an output region and having a control region therein by which said access switching means is capable of being directed, through electrical energization thereof, to effectively provide a conductive path of a selected conductivity between said access switching means input and output regions, said access switching means control region being adapted for electrical connection to a first source of control signals, said access switching means input region being electrically connected to said signal subsample input;
an input capacitance means having first and second terminal regions with said input capacitance first terminal region being electrically connected to said access switching means output region, said input capacitance second terminal region being adapted for electrical connection to a second source of control signals;
an accumulation switching means having an input region and an output region and having a control region therein by which said accumulation switching means is capable of being directed, through electrical energization thereof, to effectively provide a conductive path of a selected conductivity between said accumulation switching means input and output regions, said accumulation switching means control region being adapted for electrical connection to a third source of control signals, said accumulation switching means input region being electrically connected to said input capacitance means first terminal region;
an accumulation capacitance means having first and second terminal regions, said accumulation capacitance means first terminal region being electrically connected to said accumulation switching means output region, said accumulation capacitance means second terminal region being adapted for electrical connection to a first source of voltage;
and
an output transfer switching means having an output region and having first and second control regions therein by which said output transfer switching means is capable of being directed, through electrical energization thereof, to effectively provide a representation at said output region thereof of a signal occurring on said second control region thereof for a signal on said first control region having a value beyond a selected threshold value, said output transfer switching means first control region being adapted for electrical connection to a fourth source of control signals, said output transfer switching means second control region being electrically connected to said accumulation capacitance means first terminal region, said output transfer switching means output region being electrically connected to said accumulated sample output.

3 more elements

Dependencies are inferred from the claim text.

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Abstract

directing electromagnetic radiation from a selected portion of said field of view to move across and impinge successively on each said photodetector means in said array in that order in which said photodetector means occur in said array;
providing at an output of each of said photodetector means a sequence of corresponding photodetector output indicator values with each of said photodetector output indicator values of a said photodetector means representing that amount of said electromagnetic radiation that has impinged on that photodetector means during at least part of that selected dwell duration which has elapsed since that photodetector means provided its immediately previous photodetector output indicator value;
providing during each said dwell duration conductive signal paths alternatively between each of said photodetector means outputs and inputs of a plurality of acceptance means through an input bus interconnection means electrically connected therebetween, said plurality of acceptance means each being capable of receiving over a said conductive signal path through said input bus interconnection means a representation of a said photodetector output indicator value and storing same;
providing a subsample transfer signal path through each of a plurality of subsample transfer interconnection means each electrically connected between an output of a said acceptance means in said plurality thereof and an input of a corresponding one of a plurality of accumulation means after each receipt by that said acceptance means of a said representation of a said photodetector output indicator value, said plurality of accumulation means each being capable of receiving over its subsample transfer signal path through its corresponding subsample transfer interconnection means a transfer representation of each of those said representations of said photodetector output signal indicator values received by its corresponding acceptance means, and each being further capable of combining each said subsample transfer representation received thereby in a selected accumulation number of said dwell durations, forming an accumulation period, with any said subsample transfer representations previously received in that said accumulation period to thereby provide at an output thereof a sequence of photodetector combination indicator values with each of said photodetector combination indicator values in said plurality thereof being provided in a final said dwell duration contained in each said accumulation period;
and
providing in each said final dwell duration in each said accumulation period of each accumulation means a representation of said photodetector combination indicator value at an output of a corresponding one of a plurality of sample transfer interconnection means, said sample transfer interconnection means each having its said output electrically connected to an output bus interconnection means and an input thereof electrically connected to said output of its corresponding said accumulation means.

3 more elements