Circuit simulation method with clock event suppression for debugging LSI circuits

A logic simulation method for computing, by means of a computer, the variation of the output of at least one latch of a clock-synchronized logic circuit which includes a combination logic circuit having a plurality of logic gates and which is connected to receive at least one input signal and a plurality of clock signals of different phases, said latch being responsive to the output of said combination logic circuit in response to the rise or fall of said clock signals for latching said combination circuit output, comprising the steps of:

• (a) determining whether the outputs of said logic gates have the value 0 to 1 and determining a function of the signal values of one of said clock signals, on the basis of the initial value of said input signal, the logic function of each of said logic gates, and connection information between each of said logic gates and another logic gate or clock signal source;
• (b) calculating the output of each of said logic gates at each of a plurality of sampling instants for each of a plurality of machine cycles which coincide with the rise or fall of a first phase clock signal, including judging whether or not said input signal has varied during a time period between sampling instants, and calculating said outputs only when said input signal has varied for such one of said logic gates as is possibly susceptible to the influences of the variation of said input signal;
• (c) calculating the output of said latch at each of said sampling points from both the value of such outputs calculated at said step (b) as have been inputted to the latch and a predetermined function to be executed by said latch at each of said sampling points, including calculating, when said output value is a function of the value of one of said clock signals, the output of said latch on the basis of the signal value, which relates to said one clock signal at each of said sampling points, and said function of the latch;
• and
• (d) repeating said steps (b) and (c) in response each of the clock signals of different phases.