Leading edge detector/reply quantizer

In a pulse code communications system having a receiver, a video detector producing a composite video signal which may be formed by interfering pulse signals received by said receiver and a leading edge detector/pulse quantizer for processing said composite video signal to separate interfering pulses therein, said leading edge detector including:

• a source of clock signals;
• means responsive to the amplitude and rate of change of amplitude of said composite video signal to provide:
• (a) a positive slope (PS) signal which persists during the time said rate of change of amplitude increases at a predetermined rate;
• (b) a negative slope (NS) signal which persists during the time said rate of change of amplitude decreases at a predetermined rate;
• and
• (c) a quantized video (QV) signal which persists during the time said amplitude exceeds a predetermined level;
• a first shift register for propagating said PS signals according to their relative times of appearance;
• a second shift register for propagating said NS signals according to their relative times of appearance;
• a third shift register for propagating said QV signals according to their relative times of appearance;
• each of said first, second and third registers propagating the signals contained therein at a rate determined by said clock signals;
• first logic means for examining the contents of said first and third registers to determine the truth of a condition in which:
• said third register contains a signal which has persisted for two or more clock signals after the appearance of a first signal in said first register;
• and for inserting a signal in said first register at a position two clock signals after said first signal therein if said condition is true;
• second logic means for examining the contents of said first and second registers to determine the truth of a condition in which:
• a signal is present in said second register at a position of between 11 and 18 clock signals after a first signal appears in said first register and no second signal is present in said first register in said 11-18 clock signal interval;
• and for inserting a second signal in said first register at a position corresponding to a time of 7 clock signals before the time of appearance of said signal in said second register;
• and
• means for unloading the contents of said first register in serial-by-bit format after operation of said first and second logic means:
• the improvement wherein said first logic means further includes:
• means for determining the truth of a second condition in which:
• a first and second signal are present in said first register separated by one clock signal interval and said third register contains a signal at the time said first signal of said first register ends;
• and
• means for deleting said second signal from said first register if said second condition is not true.