US 4,897,656 AGranted

Complementary voltage interpolation circuit with transmission delay compensation

AssigneeNorth American Philips Corporation, Signetics Division

InventorsRudy J. van de Plassche, Peter G. Baltus

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Abstract

The invention centers around a system for interpolating between multiple pairs of complementary main signals to generate further pairs of complementary signals. An input circuit (10) supplies the main signals. The interpolation is a two-step operation. The first step is done with two strings (S and S.sub.N) of impedance elements (R.sub.0 -R.sub.N-1 and R.sub.N0 -R.sub.NN-1). Each pair of main signals is supplied to a corresponding pair of nodes along the strings. Interpolated signals are taken from other pairs of corresponding nodes along the strings. In the second interpolation stage, a delay network (D) formed with additional impedance elements (R.sub.D0 -R.sub.DN-1 and R.sub.DN0 -R.sub.DNN-1) compensates for transmission delays through the impedance elements that make up the strings.

Claims17

Dependent claims

An electronic circuit having input means responsive to an input parameter for providing multiple pairs of substantially complementary main signals, each of which varies with the input parameter, characterized by interpolation means comprising:

two strings of a selected number of impedance elements in which (a) a node is located between each pair of consecutive impedance elements in each string, at one end of one string, and at a corresponding end of the other string, (b) the pairs of nodes located at like positions along the strings are divided into pairs of corresponding input nodes and pairs of corresponding interpolation nodes, whereby at least one of the input nodes lies between the ends of each string, (c) at least one of the interpolation nodes is located between the two most distant input nodes in each string, and (d) each pair of corresponding input nodes receives a different one of the pairs of main signals;
and
delay means for supplying interpolation output signals at multiple pairs of corresponding interpolation output points, the number of output points being equal to the number of nodes, the delay means comprising at least two additional pairs of impedance elements for which (a) each additional pair is associated with a different pair of corresponding nodes and with a different pair of corresponding output points, (b) the impedance elements in each additional pair are coupled between the associated nodes, respectively, and the associated output points, respectively, and (c) the remaining nodes, if any, are respectively coupled to the remaining output points.

An electronic circuit for converting an analog input voltage which varies across an input voltage range into a digital code consisting of a set of most significant bits and a set of least significant bits, there being:

means for supplying the most significant bits;
means for providing a plurality of reference voltages spaced across the input voltage range;
means responsive to the input and reference voltages for generating multiple pairs of substantially complementary main signals, each having a voltage waveform that as a function of the input voltage, is of a repetitive rounded triangular shape;
and means for operating on the main signals to produce the least significant bits;
characterized in that means for operating comprises:
two strings of a selected number of impedance elements in which (a) a node is located between each pair of consecutive impedance elements in each string, at one end of one string, and at a corresponding end of the other string, (b) the pairs of nodes located at like positions along the strings are divided into pairs of corresponding input nodes and pairs of corresponding interpolation nodes, whereby at least one of the input nodes lies between the ends of each string, (c) at least one of the interpolation nodes is located between the two most distant input nodes in each string, and (d) each pair of corresponding input nodes receives a different one of the pairs of main signals;
and
delay means for supplying interpolation output signals at multiple pairs of corresponding interpolation output points, the number of output points being equal to the number of nodes, the delay means comprising at least two additional pairs of impedance elements for which (a) each additional pair is associated with a different pair of corresponding nodes and with a different pair of corresponding output points, (b) the impedance elements in each additional pair are coupled between the associated nodes, respectively, and the associated output points, respectively, and (c) the remaining nodes, if any, are respectively coupled to the remaining output points;
and
means coupled to the output points for converting the interpolation output signals into the least significant bits.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application: 07/127,867Filed 2 Dec 1987 · continuation in part
Priority: 16 Dec 1985
Granted: 30 Jan 1990
Term ends: Not estimatedThe source records don’t support an estimate.

Classification5 codes

H03M 1/205
In which one or more virtual intermediate reference signals are generated between adjacent original reference signals, e.g. by connecting…: using…
G06G 7/30
Arrangements for performing computing operations, e.g. operational amplifiers specially adapted therefor: for interpolation or extrapolation
H03M 1/141
Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit: in which at least one step…
H03M
Coding