Switched-capacitance coupling networks for differential-input amplifiers, not requiring balanced input signals

A differential delta-sigma modulator comprising:

• first and second input terminals;
• a first capacitor having respective first and second plates;
• a second capacitor having respective first and second plates;
• a differential amplifier having first and second output connections and having first and second input connections that are respectively inverting and non-inverting input connections insofar as said first output connection is concerned and are respectively non-inverting and inverting input connections insofar as said second output connection is concerned;
• a third capacitor connected between the first output connection and first input connection of said differential amplifier;
• a fourth capacitor connected between the second output connection and second input connection of said differential amplifier;
• an analog-to-digital converter for resolving the voltage between the first and second output connections of said differential amplifier to a single-bit output signal supplied in push-pull at first and second output connections thereof;
• means for generating in staggered phase relationship a first train of pulses, a second train of pulses and a third train of pulses, pulses of which said trains occur cyclically in order of their train number and do not overlap;
• means for selectively connecting the first plates of said first and second capacitors to a common-mode potential only during each pulse of said first train;
• means for selectively connecting the second plates of said first and second capacitors to said first and second input terminals, respectively, only during each pulse of said second train;
• means for selectively connecting the first plates of said first and second capacitors to the first and second input connections of said differential amplifier, respectively, only during each pulse of said third train;
• means for selectively connecting said second plates of said first and second capacitors to respective ones of the first and second output connections of said analog-to-digital converter only during intervals between pulses in said second train including times when pulses appear in said first train and times when pulses appear in said third train;
• and
• means for selectively connecting the first plates of said first and second capacitors solely to each other during each pulse of said second traind and disconnecting them from each other at least at times their second plates are connected to respective ones of the first and second output connections of said analog-to-digital converter.

A differential delta-sigma modulator for performing analog-to-digital conversions each having respective first and second portions of similar duration, said differential delta-sigma modulator comprising:

• first and second input terminals;
• a first capacitor having respective first and second plates;
• a second capacitor having respective first and second plates;
• a differential amplifier having first and second output connections and having first and second input connections that are respectively inverting and non-inverting input connections insofar as said first output connection is concerned and are respectively non-inverting and inverting input connections insofar as said second output connection is concerned;
• a third capacitor connected between the first output connection and first input connection of said differential amplifier;
• a fourth capacitor connected between the second output connection and second input connection of said differential amplifier;
• an analog-to-digital converter for resolving the voltage between the first and second output connections of said differential amplifier to a single-bit output signal supplied in push-pull at first and second output connections thereof;
• means for generating in staggered phase relationship a first train of pulses, a second train of pulses and a third train of pulses, pulses of which said trains occur cyclically in order of their train number and do not overlap;
• means for selectively connecting the first plates of said first and second capacitors to a common-mode potential only during each pulse of said first train;
• means for selectively connecting the second plates of said first and second capacitors to separate ones of said first and second terminals only during each pulse of said second train;
• means for selectively connecting the first plates of said first and second capacitors to the first and second input connections of said differential amplifier, respectively, only during each pulse of said third train in said first portions of analog-to-digital conversions;
• means for selectively connecting the first plates of said first and second capacitors to the second and first input connections of said differential amplifier, respectively, only during each pulse of said third train in said second portions of analog-to-digital conversions;
• means for selectively connecting said second plates of said first and second capacitors to separate ones of the first and second output connections of said analog-to-digital converter only during intervals between pulses in said second train including times when pulses appear in said first train and times when pulses appear in said third train, connection being one way during said first portions of analog-to-digital conversions and being the other way during said second portions of analog-to-digital conversions;
• and
• means for selectively connecting the first plates of said first and second capacitors solely to each other during each pulse of said second train and disconnecting them from each other at least at times their second plates are connected to separate ones of the first and second output connection of said analog-to-digital converter.

A differential delta-signal modulator for performing analog-to-digital conversions each having respective first and second portions of similar duration, said differential detla-sigma modulator comprising:

• first and second input terminals;
• a first capacitor having respective first and second and second plates;
• a second capacitor having respective first and second plates;
• a third capacitor having respective first and second plates;
• a fourth capacitor having respective first and second plates;
• a differential amplifier having first and second output connections and having first and second input connections that are respectively inverting and non-inverting input connections insofar as said first output connection is concerned and are respectively non-inverting and inverting input connections insofar as said second output connection is concerned;
• an analog-to-digital converter for resolving a differential voltage supplied thereto from between the first plates of said third and fourth capacitors, thereby to generate a single-bit output signal supplied in push-pull at first and second output connections thereof;
• means for generating in staggered phase relationship a first train of pulses, a second train of pulses and a third train of pulses, pulses of which said trains occurs cyclically in order of their train number and do not overlap;
• means for selectively connecting the first plates of said first and second capacitors to a common-mode potential only during each pulse of said first train;
• means for selectively connecting the first plates of said first and second capacitors to the first and second input connections of said differential amplifier, respectively, only during each pulse of said third train;
• means for selectively connecting said second plates of said first and second capacitors to separate ones of the first and second output connections of said analog-to-digital converter only during intervals between pulses in said second train including times when pulses appear in said first traain and times when pulses appear in said third train, connection being one way during said first portions of analog-to-digital conversions and being the other way during said second portions of analog-to-digital conversions;
• means for selectively connecting the first plates of said first and second capacitors solely to each other during each pulse of said second train and disconnecting them from each other at least at times their second plates are connected to separate ones of the first and second output connections of said analog-to-digital converter;
• means for selectively connecting the first and second plates of said third capacitor to the first output connection and first input connection of said differential amplifier, respectively, only during said first portions of analog-to-digital conversions;
• means for selectively connecting the first and second plates of said third capacitor to the second output connection and second input connection of said differential amplifier, respectively, only during said second portions of analog-to-digital conversions;
• means for selectively connecting the first and second plates of said fourth capacitor to the second output connection and first input connection of said differential amplifier, respectively, only during said first portions of analog-to-digital conversions;
• means for selectively connecting said fourth capacitor from the first output connection of said differential amplifier to its first input connection only during said second portions of analog-to-digital conversions;
• and
• means for selectively connecting the second plates of said first and second capacitors to separate ones of said first and second terminals only during each pulse of said second train in said first portions of analog-to-digital conversions.

A method of applying the difference between first and second input voltages to a differential delta-sigma modulator via first and second input capacitors in a switched-capacitance network, to remove the need for balancing said first and second input voltages, said method cyclically employing the following three steps in listed order;

• charging the first and second capacitors in accordance with a previous single-bit output signal from said differential delta-sigma modulator;
• connecting the first and second capacitors in series to receive the difference between the first and second input voltages for said differential delta-sigma modulator;
• and
• discharging said first and second capacitors from first plates thereof to respective terminals of a differential input circuit of said differential delta-sigma modulator while second plates of said first and second capacitors are driven in accordance with said previous single-bit output signal from said differential delta-sigma modulator.

A method of applying the difference between first and second input voltages to a differential delta-sigma modulator via first and second input capacitors in a switched-capacitance network, to remove the need for balancing said first and second input voltages, said method cyclically employing the following three steps in listed order:

• differentially charging the first and second capacitors in accordance with a previous single-bit output signal from said differential delta-sigma modulator;
• connecting the first and second capacitors in series to receive the difference between the first and second input voltages for said differential delta-sigma modulator;
• and
• discharging said first and second capacitors from first plates thereof to respective terminals of a differential input circuit of said differential delta-sigma modulator while second plates of said first and second capacitors are differentially driven in accordance with said previous single-bit output signal from said differential delta-sigma modulator.