Trilayer microlithographic process using a silicon-based resist as the middle layer

A process for applying a pattern to a workpiece used in fabricating an integrated circuit, comprising the steps of:

• depositing a thick organic layer on a surface of the workpiece;
• depositing a second layer containing an at least partially silicon-based polymer on the thick organic layer;
• depositing an organic photoresist resolution layer on the second layer;
• projecting a pattern image onto the resolution layer with a light source to which the resolution layer is sensitive;
• developing the resolution layer to leave patterned orifices therethrough and to expose patterned areas of the outer surface of the second layer;
• exposing the resolution layer and the patterned areas of the second layer to light to which the second layer is sensitive but which will be strongly absorbed by the resolution layer;
• developing the second layer to create orifices therein extending from the patterned areas of the outer surface of the second layer to corresponding patterned areas on the outer surface of the thick organic layer;
• and
• differentially etching exposed portions of the thick organic layer much faster than the second layer until the surface of the workpiece is reached.