Method and apparatus using a cache and main memory for both vector processing and scalar processing by prefetching cache blocks including vector data elements

A method of operating a digital computer, said digital computer including a vector processor, a main memory having multiple memory banks, and at least one data buffer interposed in a data path from said main memory to said vector processor, said memory storing predefined blocks of data elements at respective addresses;

• said method comprising the steps of:
• receiving an instruction to obtain a specified vector of data elements and load said vector into said vector processor,
• determining the blocks of data which include at least one data element of said vector,
• transmitting requests to reference the blocks of data which are determined to include at least one data element of said vector, and in response to those requests fetching the blocks from memory when the blocks are not stored in said data buffer, and
• obtaining from the referenced blocks said data elements of said vector and transmitting said data elements of said vector to said vector processor.

A method of operating a digital computer having a main memory, a cache, a scalar processor, and a vector processor;

• said memory including means for storing data elements at respective addresses;
• said cache including cache memory means for storing selected predefined blocks of said data elements, means for receiving requests to reference a specified block of said data, means for checking whether data for the specified block is stored in the cache memory means, and means operative when data for the specified block is not so stored for reading the specified block of data from said main memory and storing the block of data in the cache memory means;
• said method comprising the steps of:
• receiving an instruction to obtain a specified vector of said data elements and load said vector into said vector processor;
• determining the blocks of data which include at least one data element of said vector,
• transmitting to said cache requests to reference the blocks of data which are determined to include at lest one data element of said vector, and
• thereafter transmitting to said cache requests to reference individually said data elements of said specified vector, and
• transmitting said data elements of said specified vector from said cache to said vector processor.

A digital computer having a main memory and a cache coupled to said main memory;

• said main memory including means for storing data elements at respective addresses;
• said cache including cache memory means for storing selected predefined blocks of said data elements, means for receiving requests to reference a specified block of said data, means for checking whether data for the specified block is stored in the cache memory means, and means operative when data for the specified block is not so stored for reading the specified block of data from said main memory and storing the block of data in the cache memory means;
• wherein the improvement comprises:
• a vector processor coupled to said cache, said vector processor including means for receiving a sequence of data elements from said cache and performing vector operations on said data elements, and prefetch generator means coupled to said vector processor and said cache for prefetching the blocks of data which include the data elements of a vector specified by a vector load instruction, wherein said prefetch generator means includes means for receiving an instruction to obtain a specified vector of said data elements and load them into said vector processor, means for determining the blocks of data which include at least one data element of said vector, and means for transmitting to said cache requests to reference the blocks of data which are determined to include at least one data element of said vector.