"Simple code" encoder/decoder

A method for converting a ternary signal having a strong clock component into a binary signal comprising the steps of:

• extracting from the ternary signal a clock signal, a positive pulse signal corresponding to the positive values of the ternary signal, and a negative pulse signal corresponding to the negative values of the ternary signal;
• combining the positive pulse signal with the clock signal to produce an intermediate binary signal;
• and
• combining the intermediate binary signal with the negative pulse signal to produce the binary signal such that the binary signal has a high value for each positive value of the ternary signal, a low value for each negative value of the ternary signal, and an alternating high/low value for each zero value of the ternary signal.

An apparatus for converting a ternary signal having a strong clock component into a binary signal comprising:

• means for extracting from the ternary signal a clock signal, a positive pulse signal corresponding to the positive values of the ternary signal, and a negative pulse signal corresponding to the negative values of the ternary signal;
• means for combining the positive pulse signal with the clock signal to produce an intermediate binary signal;
• and
• means for combining the negative pulse signal with the intermediate binary signal to produce the binary signal such that the binary signal has a high value for each positive value of the ternary signal, a low value for each negative value of the ternary signal, and an alternating high/low value for each zero value of the ternary signal.

A method for converting a binary signal into a ternary signal on a single output line comprising the steps of:

• generating a positive value for the ternary signal when the binary signal is high for a clock period;
• generating a negative value for the ternary signal when the binary signal is low for the clock period;
• and
• generating a zero value for the ternary signal when the binary signal alternates high/low during the clock period.

A method for converting a binary signal having a strong clock component into a ternary signal comprising the steps of:

• generating from the binary signal a clock signal;
• decoding the binary signal into a positive and a negative pulse signal using the clock signal;
• and
• combining the positive and negative pulse signals to produce the ternary signal such that the ternary signal is positive when the binary signal is high for a period of the clock signal, is negative when the binary signal is low for the period of the clock signal, and is zero when the binary signal alternates high/low during the period of the clock signal.

An apparatus for converting a binary signal having a strong clock component into a ternary signal comprising:

• means for generating a clock signal from the binary signal;
• means for decoding the binary signal into a positive and a negative pulse signal using the clock signal;
• and
• means for combining the positive and negative pulse signals to produce the ternary signal such that the ternary signal is positive when the binary signal is high for a period of the clock signal, is negative when the binary signal is low for the period of the clock signal, and is zero when the binary signal alternates high/low during the period of the clock signal.