Adaptive digital network interface

A method of transmitting data units from a transmit processor over a plurality of channels comprising:

• storing a plurality of data bits of the data unit in a shift register, said shift register operable to output individual data bits;
• accessing an instruction word from a program memory, said instruction word having a plurality of fields, each containing predetermined binary values;
• shifting said data bits through said shift register in response to one of said fields containing a first predetermined binary value, said shifting operable to output a data bit for transmission on a first channel;
• and
• controlling functions of the transmit processor in response to other of said fields.

An apparatus for transmitting data units over a plurality of channels comprising:

• a first memory for storing a plurality of data bits forming a data unit, said first memory operable to serially output said data bits;
• an instruction memory for storing a plurality of instruction words in a plurality of memory locations;
• means for counting the number of data bits output from said first memory;
• means for generating a first binary control signal when the contents of said first counting means equals a first predetermined value;
• second counting means for counting the number of bits transmitted on a first channel, said bits transmitted including data bits from said first memory and non-data bits transmitted for protocol purposes;
• means for generating a second binary control signal when the contents of said second counting means equals a second predetermined value;
• sensing means for sensing the binary value of the next bit to be output from said first memory;
• means for generating a third binary control signal corresponding to said binary value of said next bit;
• and
• means for accessing an instruction in said instruction memory, said means for accessing combining said binary control signals with predetermined address bits to determined the location of a next instruction in said instruction memory.

An apparatus for transmitting serial data from a transmit processor over a plurality of multiplexed channels comprising:

• a first memory for storing a plurality of data bits, said first memory operable to serially output said data bits;
• means for accessing an instruction word from an instruction memory;
• said instruction word having a plurality of fields, said fields containing predetermined binary values;
• means for outputting a bit from said first memory in response to one of said fields containing a first predetermined binary value;
• and
• other of said fields operable to control functions of the transmitting apparatus.

A method for receiving data units over a plurality of channels comprising:

• receiving a plurality of bits, said bits including data bits forming the data units and non-data bits used for protocol information;
• accessing a first instruction stored in a program memory;
• receiving data bits in a first memory, said first memory operable to input individual bits;
• counting the number of data bits input to said first memory;
• generating a first binary control signal when the number of data bits input to said first memory equals a first predetermined value;
• counting the number of bits received on said first channel, said number of bits including said data bits and said non-data bits;
• generating a second binary control signal when the number of bits received on said first channel equals a second predetermined value;
• sensing the binary value of a next bit to be received;
• generating a third binary control signal corresponding to the value of said binary value of said next bit;
• and
• accessing a second instruction in said program memory, said second instruction located at an address determinable by combining predetermined address bits with said binary control signals.

A method of receiving data units in a receive processor over a plurality of channels comprising:

• receiving a plurality of data bits of the data units in a shift register, said shift register operable to input individual data bits;
• accessing an instruction word from a program memory, said instruction word having a plurality of fields, each containing predetermined binary values;
• shifting said data bits into said shift register in response to one of said fields containing a first predetermined binary value;
• and
• controlling functions of a receive processor in response to other of said fields.

An apparatus for receiving data units over a plurality of time-multiplexed data channels on a digital carrier comprising:

• means for receiving bits from the digital carrier, said received bits including data bits forming the data units and non-data bits used for protocol information;
• a first memory for storing a plurality of data bits, said first memory operable to serially input said data bits;
• an instruction memory for storing a plurality of instruction words in a plurality of memory locations;
• first counting means for counting the number of said data bits input to said first memory;
• means for generating a first binary control signal when the contents of said first counting means equals a first predetermined value;
• second counting means for counting the number of bits received on a first channel, said bits received including data bits and non-data bits;
• means for generating a second binary control signal when the contents of said second counting means equals a second predetermined value;
• means for sensing the binary value of a next bit to be input to said first memory;
• means for generating a third binary control signal corresponding to said binary value of said next bit;
• and
• means for accessing an instruction in said instruction memory, said means for accessing combining said binary control signals with predetermined address bits to determine the location of a next instruction in said instruction memory.

An apparatus for receiving serial data in a receiving apparatus over a plurality of multiplexed channels on a data carrier comprising:

• means for receiving the serial data from the data carrier;
• a first memory for storing a plurality of data bits, said first memory operable to serially input said data bits;
• means for accessing an instruction word from an instruction memory;
• said instruction word having a plurality of fields, each containing predetermined binary values;
• means for transferring a bit from said means for receiving to said first memory in response to one of said fields containing a first predetermined binary value;
• and
• other of said fields operable to control functions of the receiving apparatus.