US 4,881,105 AGranted

Integrated trench-transistor structure and fabrication process

AssigneeInternational Business Machines Corporation

InventorsBijan Davari, Wei Hwang, Nicky C. Lu

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Abstract

An integrated, self-aligned trench-transistor structure including trench CMOS devices and vertical "strapping transistors" wherein the shallow trench transistors and the strapping trench-transistors are built on top of buried source junctions. A p- epitaxial layer is grown on a substrate and contains an n-well, an n+ source and a p+ source regions. Shallow trenches are disposed in the epitaxial layer and contain n+ polysilicon or metal, such as tungsten, to provide the trench CMOS gates. A gate contact region connects the trenches and the n+ polysilicon or metal in the trenches. The n+ polysilicon or metal in the trenches are isolated by a thin layer of silicon dioxide on the trench walls of the gates. The p+ drain region, along with the filled trench gate element and the p+ source region, form a vertical p-channel (PMOS) trench-transistor. The n+ drain region, along with filled trench gate element and the n+ source form a vertical n-channel (NMOS) transistor. The PMOS and NMOS trench transistors are isolated by shallow trench isolation regions and an oxide layer.

An integrated, self-aligned trench-transistor structure comprising:

a substrate of semiconductor material,
a layer of epitaxial material,
a well region disposed in said epitaxial layer,
a first source element region disposed in said well region,
a second source element region disposed in said epitaxial layer proximate to said well region,
a first trench disposed in said epitaxial layer and into said first source element in said well region, said first trench being filled with conductive material to form a first gate element region,
a second trench disposed in said epitaxial layer and into said second source element region, said second trench being filled with conductive material to form a second gate element region,
a first drain element region disposed in the surface of said epitaxial layer around said first filled trench,
a second drain element region disposed in the surface of said epitaxial layer around said second filled trench,
said first filled trench gate element region, said first source element region and said first drain element region forming a first conductivity type vertical transistor,
said second filled trench gate element region, said second source element region and said second drain element region forming a second conductivity type vertical transistor,
a region of conductive material connecting said conductive gate material in said first trench and said conductive gate material in said second trench,
a third trench disposed in said epitaxial layer and into said first source element region in said well region proximate to said first trench, said third trench being filled with conductive material to form a third gate element region, and
a third drain element region disposed in the surface of said epitaxial layer around said third trench,
said third trench gate element region, said first source element region and said third drain element region forming a first conductivity type vertical trench strapping transistor for providing bias signal to said first source element region.

12 more elements

Abstract

Claims11