Method and device for the redundant control of a power controlled unit

A redundant logic circuit comprising first and second logic circuits each having a first input to which a binary logic signal is applied and an output, and a third logic circuit having inputs connected to the respective outputs of the first and second logic circuits, said first and second logic circuits respectively providing first and second output binary logic signals which are first and second respective functions of said binary logic signal and said third logic circuit providing a third output binary logic signal which is a third logic function of both said first and second output signals, the output signal of said third logic circuit being, in a normal mode of operation in which no failure is present in the redundant logic circuit, identical to said binary logic signal, whereas, when a failure is present in the redundant logic circuit, said failure having the effect of forcing to a predetermined logic level the output of either one of said first and second logic circuits, the other one of said first and second logic circuits will provide an output signal which is either identical to said binary logic signal, or the logic complement of said binary logic signal, said first logic circuit having a second input which is connected to the output of said second logic circuit and said second logic circuit having a second input which is connected to the output of said first logic circuit and said first and second logic functions together forming the inverse function of said third function.