Programmable sequence controller with operation codes partially supplying jump to addresses of machine language instruction
AssigneeHitachi, Ltd.
InventorsNaohiro Kurokawa, Ryoichi Abe
Life of this patent
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Abstract
Machine language instructions corresponding to sequence instructions that are stored in a first memory are stored at addresses of a second memory corresponding to operating codes of the sequence instructions, and a processing unit executes a sequence control by the instructions fetched from the second memory. A jump instruction with non-designated jump-to address is stored in the second memory. Following fetching of the jump instruction from the second memory, the processing unit fetches the sequence instruction to be next executed from the first memory, and the operation code of that sequence instruction is transferred to the processing unit as a jump-to address of the jump instruction.
Claims6
A programmable sequence controller, comprising:
- first read/write memory means for storing therein a sequence program provided by the user and including a combination of sequence instructions having different operation codes corresponding to different functions;
- second memory means storing therein a plurality of different machine language instructions, corresponding to said different functions of said sequence instructions, at addresses that are an arithmetic combination of a single number and said operation codes of said sequence instructions respectively;
- said second memory means storing therein, at a head address, a head jump instruction with a non-designated jump-to address;
- said second memory means storing therein a jump to said head address as a terminal part of each of said machine language instructions;
- processing means for processing said sequence program on the basis of said machine language instructions fetched from said second memory means to produce operation results;
- and
- instruction transfer means for reading out the sequence instruction to be executed from said first memory means and transferring the operation code of the sequence instruction to be executed to said processing means as part of the jump-to address of said head jump instruction;
- said processing means executing said head jump instruction with the jump-to address that is the arithmetic combination of said single number and said operation code of the sequence instruction to be executed to jump to and execute the machine language instruction corresponding to the sequence instruction to be executed;
- input means for transferring input signals from outside the controller into said processing means;
- output means for transferring an operation result of said processing means to external equipment;
- and
- address bus means and data bus means interconnecting said first and second memory means, said processing means, said instruction transfer means, said input means, and said output means.
Dependencies are inferred from the claim text.