US 4,876,660 A · Fixed-point multiplier-accumulator architecture

Abstract

An integrated circuit multiplier-accumulator architecture includes an M-bit wide register for inputting an X operand and an N-bit wide input register for inputting a Y operand to a multiplier. The multiplier can selectably multiply or concatenate the operands to produce a binary product in the form of a first array of M+N parallel bits. A binary adder adds the binary product to a second array of M+N+P+1 parallel bits and outputs the sum as a Z result in the form of a third array of M+N+P+1 parallel bits. The Z result is stored in a selected one of two accumulators. A feedback path is provided to output selected accumulator contents to the adder as the second binary array of M+N+P+1 bits. Output ports are provided for outputting a selected portion of the accumulator contents. Preferably, the output ports can output the entire M+N+P bits in parallel, as well as any selected portion thereof. Overflow logic can be provided which determines from the (M+ n+P+1)th bit whether an overflow has occurred in the M+N+P bit result. A format adjust circuit is provided between the accumulators and the output ports for shifting the entire output accumulator contents a predetermined number of bits within a range of zero to at least P bits, and preferably P+1 bits, in the direction of the most significant bit.

Claims33

Dependent claims

In an integrated circuit, a multiplier-accumulator architecture comprising:

first data input means for inputting a binary X-ray operand comprising an array of M parallel bits wherein M is an integer greater than 2;
second data input means for inputting a binary Y-operand comprising an array of N parallel bits wherein N is an integer greater than 2;
binary multiplier means for multiplying the X-operand and the Y-operand to produce a binary product in the form of a first array of M+N parallel bits;
binary adder means for adding the binary product to a second binary array of M+N+P+1 parallel bits and outputting a Z result in the form of a third array of M+N+P+1 parallel bits, where P is a predetermined non-zero number of added bits and said 1 bit is a most significant bit;
each array being ordered from most significant to the least significant bit;
accumulator means for storing the Z result including the most significant bit as accumulator contents;
feedback means for outputting the accumulator contents to the adder means as said second binary array of M+N+P+1 bits;
and
output means for outputting a selected portion of the least significant M+N+P bits of the accumulator contents.

6 more elements

In an integrated circuit, a multiplier-accumulator architecture comprising:

first data input means for inputting a binary X-operand comprising an array of N parallel bits;
second data input means for inputting a binary Y-operand comprising an array of M parallel bits;
binary multiplier means for multiplying the X-operand and the Y-operand to produce a binary product in the form of a first array of N+M parallel bits;
binary adder means for adding the binary product to a second binary array of M+N+P parallel bits and outputting an intermediate Z result in the form of a third array comprising M+N+P parallel bits, where P is a predetermined non-zero number of added bits;
each array being ordered from most significant to the least significant bit;
accumulator means for storing the intermediate Z result as accumulator contents;
feedback means for outputting the accumulator contents via a feedback path to the adder means as said second binary array;
output means for outputting the accumulator contents from the feedback path as a final Z result;
format instruction means for inputting a format adjust instruction;
format adjust means positioned to receive the final Z result output from the accumulator means and responsive to the format adjust instruction for shifting the entire final Z result a predetermined number Q of bits within a range of zero to at least P bits in the direction of the most significant bit to produce a W result of N+M+P parallel bits;
and
output means for outputting the W result from the multiplier-accumulator.

9 more elements

In an integrated circuit, a multiplier-accumulator architecture comprising:

first data input means for inputting a binary X-operand comprising an array of N parallel bits wherein N is an integer greater than or equal to 1;
second data input means for inputting a binary Y-operand comprising an array of M parallel bits wherein M is an integer greater than or equal to 1;
binary multiplier means for multiplying the X-operand and the Y-operand to produce a binary product in the form of a first array of M+N parallel bits;
binary adder means for adding the binary product to a second binary array of M+N+P parallel bits and outputting an intermediate Z result in the form of a third array comprising M+N+P parallel bits, where P is a predetermined non-zero number of added bits;
each array being ordered from most significant to the least significant bit;
accumulator means for storing the intermediate Z result as accumulator contents;
feedback means for outputting the accumulator contents to the adder means as said second binary array;
output means for outputting the accumulator contents as a final Z result from the multiplier-accumulator;
means for inputting a load instruction into the multiplier means;
and
load means in the multiplier means responsive to the load instruction for concatenating the X operand and Y operand without multiplying said operands to produce a result in which the M most significant bits are the X operand and the N least significant bits are the Y operand.

8 more elements

In an integrated circuit, a multiplier-accumulator architecture comprising:

first data input means for inputting a binary X-operand comprising an array of N parallel bits wherein N is an integer greater than or equal to 1;
second data input means for inputting a binary Y-operand comprising an array of M parallel bits wherein M is an integer greater than or equal to 1;
binary multiplier means for multiplying the X-operand and the Y-operand to produce a binary product in the form of a first array of M+N parallel bits;
binary adder means for adding the binary product to a second binary array of M+N+P parallel bits and outputting an intermediate Z result in the form of a third array comprising M+N+P parallel bits, where P is a predetermined non-zero number of added bits;
each array being ordered from most significant to the least significant bit;
accumulator means for storing the intermediate Z result as accumulator contents;
feedback means for outputting the accumulator contents to the adder means as said second binary array;
and
output means for outputting the entire accumulator contents as a final Z result from the multiplier-accumulator, said output means being separate from the first and second data input means so that new operand data can be input while the result is output at the output means to enhance throughput;
the output means including first output means for outputting the M most significant bits, second output means for outputting the N most significant bits, and third, extended output means for outputting the P least significant bits of the accumulator contents so that the least significant bits of the final Z result are retained and available for output.

7 more elements

Dependencies are inferred from the claim text.

Fixed-point multiplier-accumulator architecture

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Fixed-point multiplier-accumulator architecture

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Abstract

Claims33