Scientific processor to support a host processor referencing common memory

For use in a data processing system having host processor means and a high performance storage unit coupled to the host processor for providing high speed storage of data operands and instruction words, the host processor operable to execute instructions and control functioning of the data processing system, an improved scientific processor operable under control of the host processor comprising:

• interface means for coupling to the high performance storage unit for receiving data operands and instruction words from the high performance storage unit and for transmitting resultant data operands to the high performance storage unit;
• unit control and timing means coupled to said interface means for providing timing and control signals for synchronizing operation with the operation of the host processor and the high performance storage unit;
• local store means coupled to said interface means and coupled to said unit control and timing means for temporarily storing control parameters, data operands and instruction words received from said interface means and for at least temporarily storing resultant data operands for transmission through said interface means to the high performance storage unit;
• scalar processor module means coupled to said unit control and timing means and to said local storage means for performing scalar instruction data processing, said scalar processor module means including instruction buffer means for providing instruction word buffering between the high performance storage unit and the scientific processor;
• and
• vector process module means coupled to said unit control and timing means and coupled to said local store means for performing vector data processing instructions, said vector processor module means including a plurality of pipeline means coupled to said interface means for receiving data transfers of said data operands therefrom and for providing resultant operands thereto, and further including a plurality of vector register means for temporarily storing selected ones of said data operands and said resultant operands;
• wherein both scalar operands and vector operands can be efficiently manipulated in various combinations under program control of the host processor and to make resultant data operands available to the high performance storage unit all without the requirement of dedicated or cached memory.

For use in a data processing system having a host processor and a high performance storage unit coupled to the host processor for providing high speed storage of data operands and instruction words, the host processor operable to execute instructions and control functioning of the data processing system, an improved scientific processor operable under control of the host processor comprising:

• interface means for coupling to the high performance storage unit for receiving data operands and instructions words from the high performance storage unit and for transmitting resultant data operands to the high performance storage unit;
• unit control and timing means coupled to said interface means for providing timing and control signals for synchronizing operation with the operation of the host processor and the high performance storage unit;
• local storage means coupled to said interface means and coupled to said unit control and timing means for temporarily storing data operands and instruction words received from said interface means and for at least temporarily storing resultant data operands for transmission through said interface means to the high performance storage unit;
• scalar processor module means coupled to said unit control and timing means and to said local store means for performing scalar instruction data processing, said scalar processor means including instruction execution means and addressing means for accessing the high performance storage unit, and further including instruction buffering means for providing instruction word buffering between the high performance storage unit and the scientific processor;
• and
• vector processor module coupled to said unit control and timing means and coupled to said local storage means for performing vector data processing instructions, said vector processor module means having a plurality of vector operand manipulation pipelines operable simultaneously and each capable of providing resultant operands at rates relating to a memory reference cycle of the high performance storage unit, and further including a plurality of vector register means for temporarily storing selected ones of said data operands and said resultant operands;
• and
• where both scalar operands and vector operands can be efficiently manipulated in various combinations under program control of the host processor and to make resultant data operands available to a high performance storage unit all without the requirement of dedicated or cached memory.

In a scientific data processing system with a general purpose host processor and a main storage system having a directly coupled thereto an improved scientific processor having balanced computation and storage data transfer rates, the scientific processor comprising:

• scalar processing means for performing scalar manipulations including instruction buffer means for storing instruction words to be performed by the scientific processor;
• interface means bidirectionally coupled to said scalar processing means and adapted for coupling to the main storage system for receiving instruction words and storing them in said instruction buffer means, and for receiving and transmitting scalar and vector data operands therebetween;
• a plurality of vector registers coupled to said interface means for storing vector data operands;
• a plurality of arithmetic pipeline means coupled via said interface means to said plurality of vector registers for receiving vector data operand transfers therefrom and providing vector data operand transfers thereto;
• wherein the total concurrent vector data operand transfer between said plurality of vector registers and said plurality of arithmetic pipeline means provides a computational rate which is matched to the storage rate of data operands transferred between the improved scientific processor and the main storage system.

For use in a data processing system having a host processor and a high performance main storage system, a scientific processor with balanced computational and storage rate comprising:

• scalar processor means for performing scalar calculations;
• common interconnection means bidirectionally coupled to said scalar processor means for coupling to the higher performance main storage system;
• a plurality of arithmetic pipeline means coupled to said common interconnection means for receiving data transfers therefrom and for providing data transfers thereto;
• a plurality of vector registers coupled to said plurality of arithmetic pipelines and coupled to said common interconnection means for receiving and temporarily storing data transfers from said plurality of arithmetic pipelines and for providing data transfers thereto;
• said plurality of vector registers also adapted for coupling to the high performance main storage system for receiving stored data transfer therefrom;
• and
• an instruction buffer adapted for coupling to the high performance main storage system and to said plurality of vector registers to provide instruction buffering between the high performance main storage system and said plurality of vector registers wherein the scientific process or is balanced with the same number of computational result words per high performance main storage system cycle as the numbers of words per high performance main storage system cycle transferred from said common interconnection means.