Digital pulse generator having a programmable pulse width and a pulse repetition interval

A pulse generator for producing a pulsed output signal having a pulse width (PW) and pulse repetition interval (PRI) which are independently controllable and referenced to an external clock signal having a pulse rep rate of f.sub.c, said generator comprising:

• first counter means for counting the number of pulses in said external clock signal and for generating a first digital signal directly related to the number of counted pulses, said counter means including first resetting means for resetting said first counter means to a zero count;
• second counter means for counting the number of pulses in said external clock signal and for generating a second digital signal directly related to the number of counted pulses, said counter means including second resetting means for resetting said second counter means to a zero count and means for disabling said second counter means;
• first comparator means for producing a start pulse signal when the count represented by said first digital signal equals a first predetermined number, N.sub.1, where N.sub.1 =(PRI)(f.sub.c), said start pulse triggering said first resetting means to reset said first counter means;
• second comparator means for producing an end pulse signal when the count represented by said second counter means equals a second predetermined number, N.sub.2, where N.sub.2 =(PW)(f.sub.c), said end pulse triggering said second resetting means to reset said second counter means to reset;
• and,
• bistable circuit means connected to said first and second comparator means and capable of being toggled by said start pulse signal and by said end pulse signal, said bistable circuit means generating a single pulse signal for the time interval between said start and said end pulse signals, and said bistable circuit means disabling said second counter means for the time interval between every end and start pulse signals.

A pulse generator for producing a periodic pulse output signal f.sub.4 (t) having a pulse width (PW) and pulse repetition interval (PRI) which are accurately and independently controllable through first and second external control signals, and having a time base accuracy referenced to an external digital clock signal, f.sub.1 (t), having a very stable pulse repetition rate f.sub.c, said generator comprising:

• first counter means receiving said clock signal and counting the pulses therein, said first counter means generating a second digital signal, f.sub.2 (t), directly related to the number of counted pulses in said f.sub.1 (t), said counter means including first resetting means for resetting said first counter means to a zero count;
• second counter means receiving said clock signal and counting the pulses therein, second counter means generating a third digital signal, f.sub.3 (t), directly related to the number of counted pulses in said f.sub.1 (t), said second counter means including second resetting means for resetting said second counter means to a zero count and enabling means for enabling said second counter means;
• first comparator means receiving said second digital signal and first external control signal, said comparator means comparing the number of pulses represented by said f.sub.2 (t) with the number represented by N.sub.1, where N.sub.1 is determined by said first external control signal, and producing a start pulse signal when the number represented by f.sub.2 (t) and N.sub.1 are equal, said start pulse signal coupled to said first resetting means for triggering the reset;
• second comparator means receiving said third digital signal and second external control signal, said comparator means comparing the number of pulses represented by said f.sub.3 (t) with the number represented by N.sub.2, where N.sub.2 is determined by said second external control signal, and producing an end pulse signal when the number represented by f.sub.3 (t) and N.sub.2 are equal, said end pulse signal coupled to said second resetting means for triggering the reset;
• and,
• bistable circuit means capable of being toggled by said start pulse signal and by said end pulse signal, said bistable circuit means generating said periodic output pulse signal f.sub.4 (t), each output pulse of f.sub.4 (t) having a pulse width controlled by the time difference between said start and said end pulse signals, said output pulse being coupled to said enabling means for periodically enabling said second counter means during the time interval of each of sad output pulses.

A pulse generator for producing a periodic pulse output signal, each pulse of which has a pulse width (PW) and a pulse repetition interval (PRI) which are independently controllable and referenced to an external clock signal having a pulse rep rate of f.sub.c, said generator comprising:

• a first digital counter having a first CLK input receiving said external clock signal, said first digital counter generating a first BCD output signal corresponding to the number of counted clock pulses, said digital counter including a first reset input for resetting said first counter to a zero count;
• a second digital counter having a second CLK input receiving said external clock signal, said second digital counter generating a second BCD output signal corresponding to the number of counted clock pulses, said second digital counter including a second reset input for resetting said second counter to a zero count and an enable input for enabling said second counte;,
• a first digital comparator receiving said first BCD output signal and generating a start pulse signal whenever the count represented by said first BCD signal equals a predetermined count N.sub.1, where N.sub.1 =(PRI)(f.sub.c), said start pulse signal coupled to said first reset input for resetting said first counter;
• a second comparator receiving said second BCD output signal and generating an end pulse signal whenever the count represented by said second counter equals a predetermined count N.sub.2, where N.sub.2 =(PW)(f.sub.c), said end pulse signal coupled to said second reset input for resetting said second counter;
• and,
• a J-K flip-flop having J and K inputs and a Q output, said J and K inputs receiving said start and end pulse signals for toggling said flip-flop, said flip-flop generating at the Q output said desired periodic pulse signal, each pulse of which is determined by the time interval between said start and said end pulses, said Q output coupled to said enable input for enabling said second counter only for the time interval of each pulse of said desired output pulses.