Self-correcting digitally controlled timing circuit

A circuit for producing an output signal the time of occurrence of which is delayed with respect to an input signal applied thereto comprising:

• first means, responsive to an input signal, for generating a sequence of first signals and including adjustable delay means for controllably adjusting the lapse of time between successive ones of said first signals;
• second means, coupled to said first means, for producing an output signal in response to said first means generating a prescribed number of said first signals after receipt of an input signal by said first means;
• and
• third means, coupled to said first and second means, for controllably adjusting the lapse of time between successive ones of said first signals in accordance with a prescribed relationship between the length of time elapsed between an input signal and the production of an output signal by said second means and a reference length of time;
• said third means includes means, coupled to receive said input signal and said output signal, for generating a second signal representative of whether or not said output signal is generated by said second means prior to receipt of a further input signal by said first means.

A circuit for producing an output signal the time of occurrence of which is delayed with respect to an input signal applied thereto comprising:

• an input terminal to which an input signal is applied;
• an output terminal from which an output signal corresponding to a delayed version of said input signal is to be derived;
• a plurality of delay elements, the delay period of a respective one of which is adjustable, coupled between said input terminal and said output terminal;
• first means, coupled to said input terminal and said plurality of delay elements, for generating a sequence of first signals the lapse of time between successive ones of which is established by delays imparted by elements of said plurality;
• second means, coupled to said first means, for measuring the length of time required for said first means to generate a prescribed number of said first signals after receipt of an input signal by said first means;
• third means, coupled to said plurality of delay elements, for controllably setting the delay periods thereof;
• and
• an up/down counter the contents of which are controllably incremented or decremented in accordance with whether the length of time between a respective one of said periodically occurring signals and said second signal exceeds the length of time between successive ones of said periodically occurring signal, coupled to said second and third means, for controllably adjusting the delay period of each of said delay elements in accordance with a prescribed relationship between the length of time measured by said second means and a reference length of time.

A circuit for producing an output signal the time of occurrence of which is delayed with respect to an input signal applied thereto comprising:

• an input terminal to which an input signal is applied;
• a first flip-flop having a first input for setting said flip-flop to a first state connected to said input terminal;
• said first flip-flop having a non-inverted output terminal and an inverted output terminal;
• a first delay device having an input terminal connected to said non-inverted output terminal for receiving a signal therefrom and an output terminal connected to a second input terminal of said first flip-flop for resetting said flip-flop;
• a second flip-flop having a first input terminal for setting said second flip-flop connected to said non-inverting output terminal;
• a second delay device having an input terminal connected to an inverting output terminal of said second flip-flop for receiving a signal therefrom and an output terminal connected to a second input of said second flip-flop for resetting said second flip-flop;
• a third delay device having an input terminal connected to a non-inverting output terminal of said second flip-flop for receiving a signal therefrom and an output terminal connected to a third input of said second flip-flop for setting said second flip-flop;
• and
• shift register means having a data input terminal connected to a fixed logic level and a shift input terminal connected to said inverted output terminal of said second flip-flop for shifting said fixed logic level from said input terminal to an output terminal thereof;
• whereby said input signal sets said first flip-flop and an output signal of said first delay device resets said first flip-flop after a first preselected delay, said second flip-flop is set by an output signal on said inverted output terminal of said first flip-flop by a resetting thereof, said second delay device resets said second flip-flop after a second preselected delay, said third delay device sets said second flip-flop in response to a resetting thereof after a third preselected delay, which forms a self perpetuating oscillator having a preselected cycle time, and said shift register means shifts said fixed logic level by a multiple of said preselected cycle time to said output terminal thereof thereby delaying the output of said fixed logic level output by said multiple of preselected cycle times.