Module for packaging semiconductor integrated circuit chips on a base substrate

An integrated circuit chip packaging structure comprising:

• a substrate;
• alternating insulation and conductive layers on said substrate;
• at least two of said conductive layers being patterned conductive layers having substantially parallel, coplanar spaced apart conductive lines thereon;
• a personalized conductive reference structure having insulating regions extending at least partially through the body of said personalized reference structure at predetermined locations;
• said predetermined locations of said insulating regions coinciding with the locations of selected portions of the subsequent overlying patterned conductive layer;
• said reference structure being located above said base substrate and below a pair of patterned conductive layers in said package;
• interlayer connections between selected lines of at least two of said patterned conductive layers.

A packaging structure comprising:

• a substrate;
• alternating insulation and conductive layers on said substrate, the uppermost layer being a conductive layer;
• said insulation layers being formed of material selected from the group of organic dielectrics having active hydrogen atoms;
• at least two of said conductive layers being patterned conductive layers having substantially coplanar spaced apart power and signal lines on each layer;
• said power lines of each patterned conductive layer being substantially parallel to said signal lines on the same layer;
• each of said substantially coplanar signal lines being separated from each other by at least one substantially coplanar power line;
• stepped conductive vias comprising a dielectric mound having metallization thereon;
• said metallization electrically interconnecting selected portions of said patterned conductive layers;
• a personalized conductive reference structure having insulating regions extending at least partially through the body of said personalized reference structure at predetermined locations;
• said predetermined locations of said insulating regions coinciding with the locations of selected portions of the subsequent overlying patterned conductive layer;
• said reference structure being located above said substrate and below a pair of patterned conductive layers in said package.

An integrated circuit chip packaging structure comprising:

• a substrate;
• alternating insulation and conductive layers on said substrate;
• at least two of said conductive layers being patterned conductive layers having substantially parallel, coplanar, spaced apart conductive lines thereon;
• said patterned conductive layers being interconnected by stepped conductive vias;
• said vias comprising a mound of dielectric material having metallization thereon, said metallization interconnecting two patterned conductive layers.

An integrated circuit chip packaging structure comprising:

• a substrate;
• alternating insulation and conductive layers on said substrate;
• at least two of said conductive layers being patterned conductive layers having substantially parallel, coplanar, spaced apart conductive lines thereon;
• at least one of said insulation layers being formed of dielectric material selected from the group of organic dielectrics having active hydrogen atoms.