US 4,866,304 AGranted

BICMOS NAND gate

AssigneeMotorola, Inc.

InventorRuey J. Yu

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Abstract

A BICMOS NAND gate has P channel transistors, N channel transistors, and NPN transistors. The NPN transistors and the P channel transistors combine to provide logic high drive which avoids having the comparatively slow P channel transistors tied together. The P channel transistors are combined with NPN transistors to avoid the accumulation of capacitance that must be driven by a P channel transistor as the number of inputs increases. This avoids the typical problem of having the P channel transistors having to drive more capacitance as the number of inputs increases.

Claims5

Dependent claims

A NAND gate comprising:

a first P channel transistor having a first current coupled to a first power supply terminal, a control electrode for receiving a first input signal, and a second current electrode;
a first NPN transistor having a first current electrode coupled to the first power supply terminal, a control electrode coupled to the second current electrode of the first P channel transistor, and a second current electrode coupled to an output node, an output signal of the NAND gate being provided on the output node;
a first resistor having a first terminal coupled to the control electrode of the first NPN transistor and a second terminal coupled to the second current electrode of the first NPN transistor;
a second P channel transistor having a first current electrode coupled to the first power supply terminal, a control electrode for receiving a second input signal, and a second current electrode;
a second NPN transistor having a first current electrode coupled to the first power supply terminal, a control electrode coupled to the second current electrode of the second P channel transistor, and a second current electrode coupled to the output node;
a second resistor having a first terminal coupled to the control electrode of the second NPN transistor and a second terminal coupled to the second current electrode of the second NPN transistor;
a third P channel transistor having a first current coupled to the first power supply terminal, a control electrode for receiving a third input signal, and a second current electrode;
a third NPN transistor having a first current electrode coupled to the first power supply terminal, a control electrode coupled to the second current electrode of the third P channel transistor, and a second current electrode coupled to the output node;
a third resistor having a first terminal coupled to the control electrode of the third NPN transistor and a second terminal coupled to the second current electrode of the third NPN transistor;
and
pull-down means, coupled between the output node and a second power supply terminal, for providing a current path between the output node and the second power supply terminal only if the first, second, and third input signals are a logic high and blocking said current path if one or a more of the first, second, and third input signals are a logic low;
said pull-down means comprising first, second and third N channel transistors connected in series between the output node and the second power supply terminal, said first N channel transistor having a control electrode for receiving the first input signal, said second N channel transistor having a control electrode for receiving the second input signal, and said third N channel resistor having a control electrode for receiving the third input signal.

9 more elements

A NAND gate comprising:

a first P channel transistor having a first current coupled to a first power supply terminal, a control electrode for receiving a first input signal, and a second current electrode;
a first NPN transistor having a first current electrode coupled to the first power supply terminal, a control electrode coupled to the second current electrode of the first P channel transistor, and a second current electrode coupled to an output node, an output signal of the NAND gate being provided on the output node;
a first resistor having a first terminal coupled to the control electrode of the first NPN transistor and a second terminal coupled to the second current electrode of the first NPN transistor;
a second P channel transistor having a first current electrode coupled to the first power supply terminal, a control electrode for receiving a second input signal, and a second current electrode;
a second NPN transistor having a first current electrode coupled to the first power supply terminal, a control electrode coupled to the second current electrode of the second P channel transistor, and a second current electrode coupled to the output node;
a second resistor having a first terminal coupled to the control electrode of the second NPN transistor and a second terminal coupled to the second current electrode of the second NPN transistor;
and
pull-down means, coupled between the output node and a second power supply terminal, for providing a current path between the output node and the second power supply terminal only if the first and second input signals are a logic high and blocking said current path if one or a more of the first and second, input signals are a logic low;
said pull-down means comprising first and second N channel transistors connected in series between the output node and the second power supply terminal, said first N channel transistor having a control electrode for receiving the first input signal and said second N channel transistor having a control electrode for receiving the second input signal.

6 more elements

A NAND gate comprising:

a first P channel transistor having a first current coupled to a first power supply terminal, a control electrode for receiving a first input signal, and a second current electrode;
a first NPN transistor having a first current electrode coupled to the first power supply terminal, a control electrode coupled to the second current electrode of the first P channel transistor, and a second current electrode coupled to an output node, an output signal of the NAND gate being provided on the output node;
a first N channel transistor having a control electrode for receiving the first input signal, a first current electrode coupled to the base of the first NPN transistor, and a second current electrode coupled to a second power supply terminal;
a second P channel transistor having a first current electrode coupled to the first power supply terminal, a control electrode for receiving a second input signal, and a second current electrode;
a second NPN transistor having a first current electrode coupled to the first power supply terminal, a control electrode coupled to the second current electrode of the second P channel transistor, and a second current electrode coupled to the output node;
a second N channel transistor having a control electrode for receiving the second input signal, a first current electrode coupled to the base of the second NPN transistor, and a second current electrode coupled to the second power supply terminal;
a third P channel transistor having a first current coupled to the first power supply terminal, a control electrode for receiving a third input signal, and a second current electrode;
a third NPN transistor having a first current electrode coupled to the first power supply terminal, a control electrode coupled to the second current electrode of the third P channel transistor, and a second current electrode coupled to the output node;
a third N channel transistor having a control electrode for receiving the third input signal, a first current electrode coupled to the base of the third NPN transistor, and a second current electrode coupled to the second power supply terminal;
and
pull-down means, coupled between the output node and a second power supply terminal, for providing a current path between the output node and the second power supply terminal only if the first, second, and third input signals are a logic high and blocking said current path if one or a more of the first, second, and third input signals are a logic low;
said pull-down means comprising fourth, fifth, and sixth N channel transistors connected in series between the output node and the second power supply terminal, said forth N channel transistor having a control electrode for receiving the first input signal, said fifth N channel transistor having a control electrode for receiving the second input signal, and said sixth N channel transistor having a control electrode for receiving the third input signal.

9 more elements

A NAND gate comprising:

a first P channel transistor having a first current coupled to a first power supply terminal, a control electrode for receiving a first input signal, and a second current electrode;
a first NPN transistor having a first current electrode coupled to the first power supply terminal, a control electrode coupled to the second current electrode of the first P channel transistor, and a second current electrode coupled to an output node, an output signal of the NAND gate being provided on the output node;
a first N channel resistor having a control electrode for receiving the first input signal, a first current electrode coupled to the base of the first NPN transistor, and a second current electrode coupled to a second power supply terminal;
a second P channel transistor having a first current electrode coupled to the first power supply terminal, a control electrode or receiving a second input signal, and a second current electrode;
a second NPN transistor having a first current electrode coupled to the first power supply terminal, a control electrode coupled to the second current electrode of the second P channel transistor, and a second current electrode coupled to the output node;
a second N channel transistor having a control electrode for receiving the second input signal, a first current electrode coupled to the base of the second NPN transistor, and a second current electrode coupled to the second power supply terminal;
and
pull-down means, coupled between the output node and a second power supply terminal, for providing a current path between the output node and the second power supply terminal only if the first and second input signals are a logic high and blocking said current path if one or a more of the first and second input signals are a logic low;
said pull-down means comprising third and fourth N channel transistors connected in series between the output node and the second power supply terminal, said third N channel transistor having a control electrode for receiving the first input signal and said fourth N channel transistor having a control electrode for receiving the second input signal.

6 more elements

A NAND gate, comprising:

a first P channel transistor having a first current coupled to a first power supply terminal, a control electrode for receiving a first input signal, and a second current electrode;
a first NPN transistor having a first current electrode coupled to the first power supply terminal, a control electrode coupled to the second current electrode of the first P channel transistor, and a second current electrode coupled to an output node, an output signal of the NAND gate being provided on the output node;
a first resistor having a first terminal coupled to the control electrode of the first NPN transistor and a second terminal coupled to the second current electrode of the first NPN transistor;
a second P channel transistor having a first current coupled to the first power supply terminal, a control electrode for receiving a second input signal, and a second current electrode;
a second NPN transistor having a first current electrode coupled to th first power supply terminal, a control electrode coupled to the second current electrode of the second P channel transistor, and a second current electrode coupled to the output node;
a second resistor having a first terminal coupled to the control electrode of the second NPN transistor and a second terminal coupled to the second current electrode of the second NPN transistor;
and
a first P channel transistor having a first current coupled to the first power supply terminal, a control electrode for receiving a third input signal, and a second current electrode;
a third NPN transistor having a first current electrode coupled to the first power supply terminal, a control electrode coupled to the second current electrode of the third P channel transistor, and a second current electrode coupled to the output node;
and
a third resistor having a first terminal coupled to the control electrode of the third NPN transistor and a second terminal coupled to the second current electrode of the third NPN transistor;
and
a first N channel transistor, a second N channel transistor, and a third N channel transistor coupled in series between the output node and a second power supply terminal, said first N channel transistor having a control electrode for receiving the first input signal, said second N channel transistor having a control electrode for receiving the second input signal, and said third N channel transistor having a control electrode for receiving the third input signal.

10 more elements

Dependencies are inferred from the claim text.

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Abstract

A NAND gate comprising:

a first P channel transistor having a first current coupled to a first power supply terminal, a control electrode for receiving a first input signal, and a second current electrode;
a first NPN transistor having a first current electrode coupled to the first power supply terminal, a control electrode coupled to the second current electrode of the first P channel transistor, and a second current electrode coupled to an output node, an output signal of the NAND gate being provided on the output node;
a first resistor having a first terminal coupled to the control electrode of the first NPN transistor and a second terminal coupled to the second current electrode of the first NPN transistor;
a second P channel transistor having a first current electrode coupled to the first power supply terminal, a control electrode for receiving a second input signal, and a second current electrode;
a second NPN transistor having a first current electrode coupled to the first power supply terminal, a control electrode coupled to the second current electrode of the second P channel transistor, and a second current electrode coupled to the output node;
a second resistor having a first terminal coupled to the control electrode of the second NPN transistor and a second terminal coupled to the second current electrode of the second NPN transistor;
a third P channel transistor having a first current coupled to the first power supply terminal, a control electrode for receiving a third input signal, and a second current electrode;
a third NPN transistor having a first current electrode coupled to the first power supply terminal, a control electrode coupled to the second current electrode of the third P channel transistor, and a second current electrode coupled to the output node;
a third resistor having a first terminal coupled to the control electrode of the third NPN transistor and a second terminal coupled to the second current electrode of the third NPN transistor;
and
pull-down means, coupled between the output node and a second power supply terminal, for providing a current path between the output node and the second power supply terminal only if the first, second, and third input signals are a logic high and blocking said current path if one or a more of the first, second, and third input signals are a logic low;
said pull-down means comprising first, second and third N channel transistors connected in series between the output node and the second power supply terminal, said first N channel transistor having a control electrode for receiving the first input signal, said second N channel transistor having a control electrode for receiving the second input signal, and said third N channel resistor having a control electrode for receiving the third input signal.

9 more elements