Remote control system, components and methods

A receiver for receiving and decoding a transmitted signal wherein a predetermined parameter is varied to carry a digital message including one or more preamble bits encoded into one or more preamble chip sequences according to a preamble followed by a plurality of information bits encoded into information chip sequences according to an information code different from said preamble code, the receiver comprising:

• (a) recovery means for recovering an output stream including said information chip sequences and output representative of said preamble chip sequences from said transmitted signal, said recovery means including detector means for providing a detector signal representative of said predetermined parameter in said transmitted signal, reference value means for providing a reference value, clock means for timing a decoding sequence of predetermined chip intervals and chip-level comparison means for comparing the average value of said detector signal during each said chip interval with said reference value and assigning a first binary value or a second binary value to each said chip interval depending on whether the average value of said detector signal during the chip interval is greater than or less than the reference value;
• (b) clock synchronization means for setting said clock means during transmission of said preamble bits to generate said decoding sequence of predetermined chip intervals in synchronization with the chip intervals of said chip sequences in said transmitted signal including means for generating plural separate sequences of chip intervals, each offset from another sequence by a predetermined offset interval, subdividing each chip interval of each said sequence into a plurality of crumb intervals, crumb-level test means for testing the detector signal for the crumb intervals in each said series against a predetermined template corresponding to a predetermined series of clock signal values, and means for selecting one of said separate series for which said detector signal in the various crumb intervals of each chip best matches said template and outputting the so-selected series of chip intervals as said decoding sequence;
• (c) decoding means for emitting information bit value signals responsive only to said information chip sequences, said decoding means being coupled to said recovery means so that said decoding means will receive said output stream from said recovery means;
• and
• (d) bit level synchronization means for initializing a bit sequence index in response to emission of an initial information bit value signal by said decoding means.

A receiver for receiving and decoding a transmitted signal wherein a predetermined parameter is varied to carry a digital message including one or more preamble bits encoded into one or more preamble chip sequences according to a preamble followed by a plurality of information bit encoded into information chip sequences according to an information code different from said preamble code, the receiver comprising:

• (a) recovery means for recovering an output stream including said information chip sequences and output representative of said preamble chip sequences from said transmitted signal, said recovery means including detector means for providing a detector signal representative of said predetermined parameter in said transmitted signal, reference value means for providing a reference value, clock means for timing a decoding sequence of predetermined chip intervals and chip-level comparison means for comparing the average value of said detector signal during each said chip interval with said reference value and assigning a first binary value or a second binary value to each said chip interval depending on whether the average value of said detector signal during the chip interval is greater than or less than the reference value;
• (b) clock synchronization means for setting said clock means during transmission of said preamble bits to generate said decoding sequence of predetermined chip intervals in synchronization with the chip intervals of said chip sequences in said transmitted signal including means for generating four separate series of said predetermined chip intervals, each offset from one another by an offset interval equal to one fourth the duration of one of said predetermined chip intervals and subdividing each chip interval in each of said four separate series into two crumb intervals, crumb-level comparison means for determining whether each of said separate series of chip intervals satisfies the condition that the values of said detector signal for the two crumb intervals in each chip interval differ from one another, and means for selecting one of said separate series of chip intervals which satisfies said condition and outputting the so-selected sequence of chip intervals as said decoding sequence of chip intervals, whereby when said preamble bits in said transmitted signal are Manchester encoded with a transmitted clock signal having alternating high and low periods each having one-half the duration of one of said chip intervals, said condition will occur for only one of said separate series of chip intervals;
• (c) decoding means for emitting information bit value signals responsive only to said information chip sequences, said decoding means being coupled to said recovery means so that said decoding means will receive said output stream from said recovery means;
• and
• (d) bit level synchronization means for initializing a bit sequence index in response to mission of an initial information bit value signal by said decoding means.

A method of transmitting and recovering digital information comprising the steps of:

• (a) transmitting a signal and varying a predetermined parameter of said transmitted signal so as to impress upon said transmitted signal a digital message including one or more preamble bits encoded into one or more preamble chip sequences according to a preamble code followed by a plurality of information bits encoded into information chip sequences according to an information code different from said preamble code;
• (b) receiving said transmitted signal and recovering therefrom an output stream including said information chip sequences and output representative of said preamble chip sequences;
• (c) passing said output stream through decoder means for emitting information bit value signals responsive to said information chip sequences, said decoding means being unresponsive to said output representing said preamble chip sequences;
• and
• (d) providing bit level synchronization for initializing a bit sequence index upon emission of an initial information bit value signal by the decoding means.

A transmitter for transmitting digital information comprising:

• (a) means for timing predetermined transmitter chip intervals;
• (b) means for generating a preamble chip signal having either a first or second binary value during each of said transmitter chip intervals and a transmitter clock signal having a predetermined series of different values for transmitter crumb intervals corresponding to division of each of said transmitter chip intervals into X equal subdivisions where X is an integer;
• (c) means for impressing both said transmitter clock signal and said preamble chip signal on a predetermined parameter of a transmitted signal so that said predetermined parameter of said transmitted signal carries said preamble chip signal encoded with said transmitter clock signal during a preamble period;
• and
• (d) means for impressing said digital information as a stream of binary chip values on said predetermined parameter of said transmitted signals so that said parameter varies between one value and another value according to said transmitter chip intervals after said preamble period.

A receiver for receiving and decoding a transmitted signal wherein a predetermined parameter is varied to carry a digital message including one or more preamble bits encoded into one or more preamble chip sequences according to a preamble followed by a plurality of information bits encoded into information chip sequences according to an information code different from said preamble code, the receiver comprising:

• (a) a recovery means for recovering an output stream including said information chip sequences and output representative of said preamble chip sequences from said transmitted signal, said recovery means including detector means for providing a detector signal representative of said predetermined parameter in said transmitted signal, reference value means for providing a reference value, clock means for timing a decoding sequence of predetermined chip intervals and chip-level comparison means for comparing the average value of said detector signal during each said chip interval of said decoding sequence with said reference value or a and assigning a first binary value or a second binary value to each said chip interval depending on whether the average value of said detector signal during the chip interval is greater than or less than the reference value;
• (b) clock synchronization means for setting said clock means during transmission of said preamble bits to generate said decoding sequence of predetermined chip intervals in synchronization with the chip intervals in said transmitted signal, said clock synchronization means including means for generating plural separate sequences of chip intervals, each offset from another sequence by a predetermined offset interval, subdividing each chip interval of each said sequence into a plurality of crumb intervals, crumb-level test means for testing the detector signal for the crumb intervals in each said series against a predetermined template corresponding to a predetermined series of clock signal values, and means for selecting one of said separate series for which said detector signal in the various crumb intervals of each chip best matches said template and outputting the so-selected series of chip intervals as said decoding sequence;
• (c) decoding means for emitting information bit value signals responsive only to said information chip sequences, said decoding means being coupled to said recovery means so that said decoding means will receive said output stream from said recovery means;
• and
• (d) bit-level synchronization means for initializing a bit sequence index.

A receiver for receiving and decoding a transmitted signal wherein a predetermined parameter is varied to carry a digital message including one or more preamble bits encoded into one or more preamble ship sequences according to a preamble followed by a plurality of information bits encoded into information chip sequences according to an information code different from said preamble code, the receiver comprising:

• (a) a recovery means for recovering an output stream including said information chip sequences and output representative of said preamble chip sequences from said transmitted signal, said recovery means including detector means for providing a detector signal representative of said predetermined parameter in said transmitted signal, reference value means for providing a reference value, clock means for timing a decoding sequence of predetermined chip intervals and chip-level comparison means for comparing the average value of said detector signal during each said chip interval with said reference value and assigning a first binary value or a second binary value to each said chip interval depending on whether the average value of said detector signal during the chip interval is greater than or less than the reference value;
• (b) clock synchronization means for setting said clock means during transmission of said preamble bits to generate said decoding sequence of predetermined chip intervals in synchronization with the chip intervals of said chip sequences in said transmitted signal, said clock synchronization means including means for generating four separate series of said predetermined chip intervals, each offset from one another by an offset interval equal to one fourth the duration of one of said predetermined chip intervals and subdividing each chip interval in each of said four separate series into two crumb intervals, crumb-level comparison means for determining whether each of said separate series of chip intervals satisfies the condition that the values of said detector signal for the two crumb intervals in each chip interval differ from one another, and means for selecting one of said separate series of chip intervals which satisfies said condition and outputting the so-selected sequence of chip intervals as said decoding sequence of chip intervals, whereby when said preamble bits in said transmitted signal are Manchester encoded with a transmitted clock signal having alternating high and low periods each having one-half the duration of one of said chip intervals, said condition will occur for only one of said separate series of chip intervals;
• (c) decoding means for emitting information bit value signals responsive only to said information chip sequences, said decoding means being coupled to said recovery means so that said decoding means will receive said output stream from said recovery means;
• and
• (d) bit-level synchronization means for initializing a bit sequence index. PG,130