US 4,864,160 A · Timing signal generator

Abstract

A timing generator for generating timing signals representing the leading and trailing edges of test pulses. In one embodiment of the invention, a period circuit repetitively measures time intervals, or periods, based on signals from a clock circuit, and a marker circuit generates timing signals representing leading edge and trailing edge markers precisely within each period. The period circuit comprises a period-end memory having a plurality of storage locations which are addressed by a modulo(n) counter. To support multiple timing sets, or timing cycles, one or more of the most significant bits of the address field for the period-end memory may be reserved for designating each timing signal. The time interval measured by the period-end memory may be selectively extended by delaying the clocking signal used for incrementing the modulo(n) counter. The marker circuit comprises leading edge and trailing edge marker memories for storing values indicating where in a period a leading edge or a trailing edge marker is generated. The marker circuit further comprises extended cycle leading edge and trailing edge marker memories for storing values indicating where in a later timing cycle a marker is to be generated. Leading edge and trailing edge marker vernier memories are provided for storing values used to indicate the exact placement of markers within the time interval. Leading edge and trailing edge end-of-cycle marker memories are used for generating leading edge and trailing edge markers at the end of a particular timing cycle. Leading edge and trailing edge marker inhibit memories are used for inhibiting marker generation within a particular timing cycle.

Claims46

Dependent claims

A circuit for generating timing signals comprising:

period means for repetitively measuring a time interval, the time interval comprising a plurality of subintervals, termed period windows, the period means comprising:
a period memory having a plurality (n) of period memory storage locations for any integer n greater than one, each period memory storage location corresponding to a period window, the plurality of period memory storage locations in the period memory being divided into groups, the plurality of period memory storage locations in each group occupying contiguous sequential addresses;
period memory address means, coupled to the period memory, for sequentially addressing the plurality of period memory storage locations;
a modulo (n) counter, coupled to the period memory, for repetitively addressing the n period memory storage locations in a prescribed sequence;
and
timing signal generating means, coupled to the period means, for generating a timing signal within a prescribed period window.

3 more elements

A circuit for generating timing signals comprising:

period means for repetitively measuring a time interval, the time interval comprising a plurality of subintervals, termed period windows, the period means comprising:
a period memory having a plurality (n) of period memory storage locations for any integer n greater than one, each period memory storage location corresponding to a period window;
period memory address means, coupled to the period memory, for sequentially addressing the plurality of period memory storage locations;
a modulo (n) counter, coupled to the period memory, for repetitively addressing the n period memory storage locations in a prescribed sequence;
and
timing signal generating means, coupled to the period means, for generating a timing signal within a prescribed period window wherein the timing signal generating means further comprises:
a first marker memory having a plurality of marker memory storage locations, each marker memory storage location corresponding to a period window;
and
marker memory address means, connected to the first marker memory, for sequentially addressing the plurality of marker memory storage locations.

6 more elements

A circuit for generating timing signals comprising:

period means for repetitively measuring a time interval, the time interval comprising a plurality of subintervals, termed period windows, the period means comprising:
a period memory having a plurality (n) of period memory storage locations for any integer n greater than one, each period memory storage location corresponding to a period window;
a modulo (n) counter, coupled to the period memory, for repetitively addressing the n period memory storage locations in a prescribed sequence;
period memory address means, coupled to the period memory, for sequentially addressing the plurality of period memory storage locations, the period memory address means including period extending means, coupled to the modulo (n) counter, for selectively extending the time interval measured by the period means;
and
timing signal generating means, coupled to the period means, for generating a timing signal within a prescribed period window.

3 more elements

Dependencies are inferred from the claim text.

Timing signal generator

Life of this patent

Timing signal generator

Life of this patent

Abstract

Claims46