Digital circuit for suppressing fast signal variations
AssigneeU.S. Philips Corporation
InventorsWolfgang Schwartz, Otto L. Warmuth, Claus D. Grzyb
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Abstract
A digital circuit which receives a serial input signal and which suppresses fast signal variations. The digital circuit includes an integrator circuit (1) which generates a multi-bit signal by integration of the serial input signal. The output signal of the integrator circuit is applied to an evaluation circuit (2) which generates a serial output signal which assumes a first state when the multi-bit signal exceeds a first threshold value and a second state when the multi-bit signal is below a second threshold value.
Claims9
A digital circuit which receives a serial input signal and which suppresses fast signal variations in said signal, said digital circuit comprising an integrator circuit which generates a multi-bit signal by integration of said serial input signal, and an evaluation circuit which derives from said multi-bit signal a serial output signal which assumes a first state when said multi-bit signal exceeds a first threshold value and a second state when said multi-bit signal is below a second threshold value, said evaluation circuit comprising logic means for combining the three most significant bits of said multi-bit signal into a control signal when said multi-bit signal exceeds said first threshold value which sets a flipflop so as to generate said serial output signal, and resets said flipflop when said multi-bit signal is below said second threshold value.
A digital circuit for producing an output signal, said circuit having as an input a serial input signal having a plurality of states, said digital circuit comprising:
- (a) means for integrating said serial input signal so as to generate a multi-bit signal, said multi-bit signal having a value representing variation in said states of said input signal.
- (b) means for evaluating said multi-bit signal and for deriving therefrom an output signal which assumes a first state when said multi-bit signal exceeds a first threshold value, and a second state when said multi-bit signal is below a second threshold value, said evaluating means comprising logic means for combining the three most significant bits of said multi-bit signal and for generating a control signal which sets a flipflop coupled thereto when said multi-bit signal exceeds said first threshold value thereby generating said serial output signal, and resets said flipflop when said multi-bit signal is below said second threshold value.
Dependencies are inferred from the claim text.