US 4,862,347 AGranted

System for simulating memory arrays in a logic simulation machine

AssigneeInternational Business Machine Corporation

InventorAnn M. Rudy

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Abstract

A method and apparatus for simulating memory devices in a logic simulation machine include a finite state machine (FSM) having input/output (I/O) sources, instruction storage resources, a real memory resource, and instruction execution resources. A plurality of memory device ports to be simulated are defined and associated with corresponding respective subsets of the I/O resources of the FSM. Permutated sets of simulated memory array access signals, such as data, address, and control, are bound to selectable ones of the simulated memory ports and stored in the FSM, with the parameters of the memory operation established by the simulated signals. Stored sets of access instructions, representative of memory access operations, are augmented by the simulated signals and executed by the FSM against the real memory resource. All array instructions representing the same memory array share the same address space in the real memory resource.

Claims10

Dependent claims

A method for simulating multi-port memory arrays, said method being executed upon a highly parallel logic simulation machine (LSM) including a memory simulator which emulates a memory array with a plurality of memory ports, said memory simulator including input and output resources, said method comprising the steps of:

providing a set of array instructions through said LSM to said memory simulator, each array instruction of said set of array instructions defining a simulated memory access operation to be performed on said memory array;
binding each array instruction of said set of array instructions to a respective memory port of said plurality of memory ports;
storing said set of array instructions in said memory simulator;
partitioning said input resources into input resource subsets, each of said input resource subsets corresponding to a respective memory port of said plurality of memory ports;
permutatively entering first simulated memory access signals from said LSM into said input resource subsets according to a permutation pattern which corresponds each first simulated memory access signal with a respective memory port of said plurality of memory ports;
in said memory simulator, executing each array instruction of said set of array instructions, using first simulated memory access signals which are stored in an input resource subset corresponding with the respective memory port to which said array instruction is bound to represent parameters of the simulated memory access operation defined by said array instruction;
producing by execution of said array instructions second simulated memory access signals, said second simulated memory access signals representing the results of simulated memory access operations performed on said memory array;
and
permutatively providing through said output resources to said LSM said second simulated memory access signals.

6 more elements

In a highly parallel logic simulation machine (LSM) which produces access instructions, a permutation pattern, and input simulated memory access signals, a memory simulation processor for simulating multiport memory, said memory simultation processor comprising:

an input memory connected to said LSM for receiving groups of input simulated memory access signals, each of said groups defining parameters for a simulated memory access operation to be conducted at a simulated port of said multiport memory;
a programmable simulation profile memory means connected to said LSM for receiving and storing a set of array instructions, each array instruction of said set of array instructions defining a simulated port and a simualted memory access operation to be conducted at said simulated port;
programmable input permutation means connected to said LSM and to said input memory for permutatively entering each of said groups of input simulated memory access signals into a respective portion of said input memory according to said permutation pattern, said permutation pattern corresponding respective portions of said input memory with a simulated port defined by a respective array instruction of said set of array instructions;
instruction execution means connected to said programmable simulation profile memory means and to said input memory for obtaining an array instruction and a group of input simulated memory access signals in a respective portion of said input memory corresponding with the simulated port defined by said array instruction, said instruction execution means including means for executing said array instruction using said group of input simulated memory access signals to produce a group of output simulated memory access signals which indicate the result of the simulated memory access operation performed by said array instruction;
and
output means connected to said LSM and to said instruction execution means for obtaining groups of output simulated memory access signals and for permutatively providing said groups of output simulated memory access signals to said LSM as simulated output of said multiport memory.

3 more elements

Dependencies are inferred from the claim text.