Package semiconductor chip

An encapsulated semiconductor module comprising;

• a semiconductor chip having terminals thereon disposed within an encapsulating material;
• a plurality of self supporting unitary, discrete, and continuous lead frame conductor and formed of metal sheet stock extending over said chip and positioned to avoid contact with said terminals and extending from said chip and cantilevered out of the encapsulating material;
• an electrically insulating material forming an alpha barrier disposed between said chip and said plurality of lead frame conductors, and attached to said plurality of lead frame conductors and to said semiconductor chip with respective adhesive layers;
• and
• discrete electrical conducting wire means respectively bonded to each conductor and each terminal and electrically connecting a respective conductor to a respective terminal.

A semiconductor modules comprising;

• a semiconductor chip having a major surface, provided with a plurality of integrated circuit devices at least partly embedded in said major surface and terminal pads on said major surface electrically coupled to said devices,
• an electrically insulating material disposed on and joined to said major surface,
• a plurality of self supporting unitary, discrete, and continuous lead frame conductors formed of metal sheet stock disposed on and joined to said material and positioned to avoid contact with said terminal pads and cantilevered from said chip,
• a plurality of discrete wire means bonded to said conductors and said terminal pads and electrically connecting respective ones of said conductors to respective ones of said terminal pads, and
• an encapsulating material disposed over and enclosing said terminal pads, said electrically insulating material and said plurality of wire means and a portion of said lead frame conductors, the remainder of leads frame conductors cantilevered out of said encapsulating material.

A semiconductor module comprising:

• a semiconductor chip having a major surface, provided with a plurality of heat generating integrated circuit devices at least partially embedded in said major surface, and with rows of terminals on said major surface electrically coupled to said devices, at least one of said rows being centrally positioned on said major surface,
• an electrically insulating and thermally conducting material disposed on and joined to said major surface, with a silicone adhesive, said material being substantially free of halides, sodium, potassium and phosphorus,
• a plurality of conductors disposed on and joined to said material with an epoxy or acrylic adhesive, said plurality of conductors collectively covering between 30% and 80% of said major surface and including at least one bus bar, said bus bar being disposed on said material over those devices that generate a major portion of the heat in said chip,
• a plurality of means joined to said conductors and to said terminals and electrically connecting respective ones of said conductors to respective ones of said terminals, said means being less than 30 mils in length, and
• an encapsulating material disposed over and enclosing said terminals, said electrically insulating material and said plurality of means and partially covering at least 0.5 mm of each of said conductors, the remainder of said conductors extending out of said encapsulating material.