Error protected central control unit of a switching system and method of operation of its memory configuration

An error protected, highly reliable multiprocessor central control unit for a switching system, comprising:

• a central bus system;
• a plurality of central processors, connected in parallel to said central bus system, for processing momentary switching assignments;
• and
• a central memory system, connected to said central bus system in parallel with said plurality of central processors, having a redundant configuration and including:
• a memory block pair, comprising:
• a first and a second memory block operating in synchronous step in parallel during normal periods of operation, apart from a possible tolerable timing slip;
• and a first and a second memory error detection and correction circuit associated with said first and second memory blocks, respectively, for protecting against errors while data are stored in said first and second memory blocks;
• and
• a memory configuration unit, connected to said memory block pair exclusive of said central bus system, and comprising:
• a first and a second configuration processor, operating in synchronous step in parallel, apart from a possible tolerable timing slip, each configuration processor controlled by commands and generating processing results;
• a first and a second processor error detection and correction circuit, associated with said first and second configuration processors, respectively, for individually checking each of said first and second processors;
• and a processor comparison circuit for continuously comparing the respective commands and/or processing results of said first and second processors;
• wherein:
• said central processors access at least a section of said memory block pair for successive read-out and write operations through said central bus system;
• and
• said memory configuration unit isolates one of said memory blocks from said central bus system in response to an indication from the memory error detection and correction circuit associated with said one of said memory blocks indicating a not-immediately-correctable failure of said one of said memory blocks, whereby the other one of said memory blocks performs said read-out and write operations with said central processors;
• and said memory configuration unit control correction of the data stored in said one of said memory blocks while said one of said memory blocks is isolated from said central bus system, after said one of said memory blocks is repaired, by reading out correct data from said other one of said memory blocks and writing said correct data into said one of said memory blocks;
• wherein, if, during this correction, a write operation to said other one of said memory blocks occurs, the data written into said other one of said memory blocks is immediately written into said one of said memory blocks.

A method of operating an error protected, highly reliable multiprocessor central control unit for a switching system, said central control unit including:

• a central bus system;
• a plurality of central processors, connected in parallel to said central bus system, for processing momentary switching assignments;
• and a central memory system, connected to said central bus system in parallel with said plurality of central processors, having a redundant configuration and including:
• a memory block pair, comprising:
• a first and a second memory block, periodically requiring refreshing, and operating in synchronous step in parallel during normal normal periods of operation, apart from a possible tolerable timing slip;
• and a first and a second memory error detection and correction circuit associated with said first and second memory blocks, respectively, for protecting against errors while data are stored in said first and second memory blocks;
• and a memory configuration unit, connected to said memory block pair exclusive of said central bus system, and comprising:
• a first and a second configuration processor, operating in synchronous step in parallel, apart from a possible tolerable timing slip, each configuration processor controlled by commands and generating processing results;
• a first and a second processor error detection and correction circuit, associated with said first and second configuration processors, respectively, for individually checking each of said first and second processors;
• and a processor comparison circuit for continuously comparing the respective commands and/or processing results of said first and second processors;
• said method comprising the steps of:
• (a) starting refreshing of said first and second memory blocks in cycles by means of said memory configuration unit;
• (b) checking and correcting the stored data read during refresh cycles by means of said first and second memory error detection and correction circuits;
• (c) if a not-immediately-correctable error is detected by a one of said first and second memory error detection and correction circuits in said checking and correcting step, beginning off-normal operation by isolating the one of said memory blocks associated with said one of said first and second memory error detection and correction circuits from said central bus system by means of said memory configuration unit;
• (d) reloading said isolated one of said first and second memory blocks with data from the other one of said first and second memory blocks, by means of said memory configuration unit;
• and
• (e) resuming normal operation after completion of said reloading step, by reconnecting said one of said first and second memory blocks to said central bus system by means of said memory configuration unit to resume said parallel synchronous operation of said memory block pair, apart from said possible tolerable timing slip.