Master/slave synchronizer

A synchronizer having a plurality of ports each connected to a device, each device operable as a slave or a master device receiving or generating a clock signal, respectively, synchronizing transmission of data through said device comprising:

• a plurality of registers (102) each having plural-bit contents received from and/or conducted to a microprocessor external to said synchronizer;
• data-routing multiplexer means (50, 108, 110) operably connected to said plurality of registers, responsive to at least a first and a second synchronizing clock signal for selectably establishing transmission paths between pairs of said ports and for transmitting data on said paths with a selectable one of said first or second synchronizing clock signals;
• and
• clock-routing means (100, 102, 104, 106) operably connected to said plurality of registers, responsive to said device clock signals for generating said first and said second synchronizing clock signals, said signals selected as said slave and said master, said master and said slave, or said slave and said slave signals, respectively.